Information for AlteraCycloneV_HPS

This page provides detailed information about the altera.ovpworld.org AlteraCycloneV_HPS Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This platform models the Altera Cyclone V SOC FPGA chip Hard Processor System.

The processor is an ARM Cortex-A9MPx2.

Limitations
Peripherals are modeled only to the extent required to boot and run Operating Systems such as Linux.

Reference
Cyclone V Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30.

Location
The AlteraCycloneV_HPS virtual platform is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / module / AlteraCycloneV_HPS / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpuarm.ovpworld.orgarmCortex-A9MPx2
PeripheralL2arm.ovpworld.orgL2CachePL310
Peripheraltimer0altera.ovpworld.orgdw-apb-timer
Peripheraltimer1altera.ovpworld.orgdw-apb-timer
Peripheraltimer2altera.ovpworld.orgdw-apb-timer
Peripheraltimer3altera.ovpworld.orgdw-apb-timer
Peripheraluart0altera.ovpworld.orgdw-apb-uart
Peripheraluart1altera.ovpworld.orgdw-apb-uart
PeripheralRSTMGR0altera.ovpworld.orgRSTMGR
PeripheralSYSMGR0ovpworld.orgdummyPort
PeripheralCLKMGR0ovpworld.orgdummyPort
Peripheralpdma0ovpworld.orgdummyPort
Peripheralgmac0ovpworld.orgdummyPort
Peripheralemac0_dmaovpworld.orgdummyPort
Peripheralgmac1ovpworld.orgdummyPort
Peripheralemac1_dmaovpworld.orgdummyPort
PeripheralsmartLoaderarm.ovpworld.orgSmartLoaderArmLinux
Memorysram1ovpworld.orgram
Bussmbus(builtin)address width:32



Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A9MPx2' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A9MPx2.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Core Features
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.

Memory System
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
VMSA secure and non-secure address translation is implemented.

Advanced SIMD and Floating-Point Features
SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Interrupt Controller
GIC block is implemented (GICv1, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register ICDDCR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register ICDDCR can be observed by monitoring address 0x80001000

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter enableSystemMonitorBus is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter enableSystemBus is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 2: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips100.0The nominal MIPS for the processor

Table 3: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantCortex-A9MPx2enum
compatibilityISAenum
UAL1bool
showHiddenRegs0bool
override_CBAR0xfffec000uns32
override_GICD_TYPER_ITLines6uns32


Memory Map for processor 'cpu' bus: 'smbus'
Processor instance 'cpu' is connected to bus 'smbus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'smbus' using master port 'DATA'.

Table 4: Memory Map ( 'cpu' / 'smbus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFFsram1ram
0xFF7000000xFF700FFFgmac0dummyPort
0xFF7010000xFF701FFFemac0_dmadummyPort
0xFF7020000xFF702FFFgmac1dummyPort
0xFF7030000xFF703FFFemac1_dmadummyPort
0xFFC020000xFFC02FFFuart0dw-apb-uart
0xFFC030000xFFC03FFFuart1dw-apb-uart
0xFFC080000xFFC08FFFtimer0dw-apb-timer
0xFFC090000xFFC09FFFtimer1dw-apb-timer
0xFFD000000xFFD00FFFtimer2dw-apb-timer
0xFFD010000xFFD01FFFtimer3dw-apb-timer
0xFFD040000xFFD04FFFCLKMGR0dummyPort
0xFFD050000xFFD05FFFRSTMGR0RSTMGR
0xFFD080000xFFD08FFFSYSMGR0dummyPort
0xFFE010000xFFE01FFFpdma0dummyPort
0xFFFEF0000xFFFEFFFFL2L2CachePL310


Net Connections to processor: 'cpu'

Table 5: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
SPI199ir199timer0dw-apb-timer
SPI200ir200timer1dw-apb-timer
SPI201ir201timer2dw-apb-timer
SPI202ir202timer3dw-apb-timer
SPI194ir194uart0dw-apb-uart
SPI195ir195uart1dw-apb-uart
reset_CPU0cpu0ResetRSTMGR0RSTMGR
reset_CPU1cpu1ResetRSTMGR0RSTMGR



Peripheral Instances


Peripheral [arm.ovpworld.org/peripheral/L2CachePL310/1.0] instance: L2

Description
ARM PL310 L2 Cache Control Registers

Licensing
Open Source Apache 2.0

Limitations
Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference
ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual (ARM DDI 0246)

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/dw-apb-timer/1.0] instance: timer0

Description
Model of dw-apb-timer for CycloneV platform.

Limitations
Only functionality required for Altera Cyclone-V is implemented: single timer, 32 bits, little endian only
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/dw-apb-timer/1.0] instance: timer1

Description
Model of dw-apb-timer for CycloneV platform.

Limitations
Only functionality required for Altera Cyclone-V is implemented: single timer, 32 bits, little endian only
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/dw-apb-timer/1.0] instance: timer2

Description
Model of dw-apb-timer for CycloneV platform.

Limitations
Only functionality required for Altera Cyclone-V is implemented: single timer, 32 bits, little endian only
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/dw-apb-timer/1.0] instance: timer3

Description
Model of dw-apb-timer for CycloneV platform.

Limitations
Only functionality required for Altera Cyclone-V is implemented: single timer, 32 bits, little endian only
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/dw-apb-uart/1.0] instance: uart0

Licensing
Open Source Apache 2.0

Description
Model of dw-apb-uart UART for CycloneV platform.

Limitations
No modeling of baudrate.
No modem support (DTR etc).
No support for parity.
No means to simulate errors.
Derived from national.ovpworld.org 16450 model. Just enough to do basic tty capabilities.
Only first 8 registers implemented.

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Table 6: Configuration options (attributes) set for instance 'uart0'

AttributesValue
outfileuart0.log
console1
finishOnDisconnect1



Peripheral [altera.ovpworld.org/peripheral/dw-apb-uart/1.0] instance: uart1

Licensing
Open Source Apache 2.0

Description
Model of dw-apb-uart UART for CycloneV platform.

Limitations
No modeling of baudrate.
No modem support (DTR etc).
No support for parity.
No means to simulate errors.
Derived from national.ovpworld.org 16450 model. Just enough to do basic tty capabilities.
Only first 8 registers implemented.

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Table 7: Configuration options (attributes) set for instance 'uart1'

AttributesValue
outfileuart1.log
console1
finishOnDisconnect



Peripheral [altera.ovpworld.org/peripheral/RSTMGR/1.0] instance: RSTMGR0

Description
Altera Cyclone V Reset Manager

Limitations
Only register mpumodrst cpu0 and cpu1 reset functionality is implemented

Licensing
Open Source Apache 2.0

Reference
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: SYSMGR0

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: CLKMGR0

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: pdma0

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: gmac0

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: emac0_dma

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: gmac1

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: emac1_dma

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/SmartLoaderArmLinux/1.0] instance: smartLoader

Licensing
Open Source Apache 2.0

Description
Psuedo-peripheral to perform memory initialisation for an ARM based Linux kernel boot: Loads Linux kernel image file and (optional) initial ram disk image into memory. Writes ATAG data into memory. Writes tiny boot code at physical memory base that configures the registers as expected by Linux Kernel and then jumps to boot address (image load address by default).

Limitations
Only supports little endian

Reference
See ARM Linux boot requirements in Linux source tree at documentation/arm/Booting

Table 8: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
boardid0xffffffff
kernelzImage
initrdfs.img
commandmem=1024M console=ttyS0
physicalbase0x00000000
memsize0x40000000
disable0



Other Sites/Pages with similar information

Information on the AlteraCycloneV_HPS Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: iGen Model Generator Introduction
http://www.ovpworld.org: Simulation Control of Platforms and Modules User Guide

Two Videos on these models (from other sites)
http://www.ovpworld.org: OR1K Demo Video Presentation
http://www.ovpworld.org: OR1K Demo Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS