Information for ArmCortexMFreeRTOS

This page provides detailed information about the imperas.ovpworld.org ArmCortexMFreeRTOS Virtual Platform / Virtual Prototype.

Description
Platform for FreeRTOS bring

Licensing
Open Source Apache 2.0

Limitations
BareMetal platform for bring up of FreeRTOS on ARM Cortex-M3 processor

Reference
www.freertos.org

Location
The ArmCortexMFreeRTOS virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / module / ArmCortexMFreeRTOS / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpu1arm.ovpworld.orgarmmCortex-M3
Peripheralledovpworld.orgledRegister
PeripheralUART0ti.ovpworld.orgUartInterface
Memorymemory1ovpworld.orgram
Memorymemory2ovpworld.orgram
Busbus1(builtin)address width:32
BuspBusMapped(builtin)address width:32
BridgepBusBridge(builtin)


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module ArmCortexMFreeRTOS

Table 3: External Ports

Port TypePort NameInternal Connection
busportpBusPpBusMapped



Processor [arm.ovpworld.org/processor/armm/1.0] instance: cpu1

Processor model type: 'armm' variant 'Cortex-M3' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/armm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_armm_Cortex-M3.pdf

Description
ARMM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.

Limitations
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.

Verification
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.

Features
The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
Thumb-2 instructions are supported.
MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
Bit-band region is present. Use parameter BitBandPresent to disable it if required.

Unpredictable Behavior
Many instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.

Equal Target Registers
Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.

Floating Point Load/Store Multiple Lists
Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.

If-Then (IT) Block Constraints
Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.

Use of R13
Use of R13 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows R13 to be used like any other GPR.

Use of R15
Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed.
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default value of "unpredictableR15" is "execute".

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu1' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips12The nominal MIPS for the processor

Table 5: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType
variantCortex-M3enum
UAL1bool


Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.

Table 6: Memory Map ( 'cpu1' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFFmemory1ram
0x400040000x40004007ledledRegister
0x4000C0000x4000CFFFUART0UartInterface
0x401000000x401FFFFFpBusBridgebridge
0x410000000xFFFFFFFFmemory2ram

Table 7: Bridged Memory Map ( 'cpu1' / 'pBusBridge' / 'pBusMapped' [width: 32] )

Lo AddressHi AddressInstanceComponent


Net Connections to processor: 'cpu1'

Table 8: Processor Net Connections ( 'cpu1' )

Net PortNetInstanceComponent
intuart_irqUART0UartInterface



Peripheral Instances


Peripheral [ovpworld.org/peripheral/ledRegister/1.0] instance: led

Description
Simple test peripheral providing a register that may be used to toggle LED outputs.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon a real device

Table 9: Configuration options (attributes) set for instance 'led'

AttributesValue
availableLEDS8



Peripheral [ti.ovpworld.org/peripheral/UartInterface/1.0] instance: UART0

Description
UART: Universal Asynchronous Receiver Transmitter This model contains an accurate Register set interface for the TI Stellaris ARM Cortex-M3 based device.

Limitations
The functionality of this model is limited. Basic status flag setting allows character reception and transmission.

Reference
FreeRTOS Cortex-M3 / GCC Port LM3S102 with GCC for Luminary Micros Stellaris microcontrollers http://www.freertos.org/portcortexgcc.html

Licensing
Open Source Apache 2.0

Table 10: Configuration options (attributes) set for instance 'UART0'

AttributesValue
console1
finishOnDisconnect1
loopback1



Other Sites/Pages with similar information

Information on the ArmCortexMFreeRTOS Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Creating & Using Platforms and Models in C++ with OP API
http://www.ovpworld.org: VMI Programmers Views (VMI VIEW) API Reference Guide.

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARC Demo Video Presentation
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
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MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS