Information for ArmCortexMuCOS-II

This page provides detailed information about the imperas.ovpworld.org ArmCortexMuCOS-II Virtual Platform / Virtual Prototype.

Description
Platform for Micrium uc/OS-II bring up and simple LED access

Licensing
Open Source Apache 2.0

Limitations
BareMetal platform for bring up of uc/OS-II on ARM Cortex-M3 processor

Reference
www.micrium.com/page/products/rtos/os-ii

Location
The ArmCortexMuCOS-II virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / module / ArmCortexMuCOS-II / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpu1arm.ovpworld.orgarmmCortex-M3
Peripheralledovpworld.orgledRegister
Memorymemory1ovpworld.orgram
Memorymemory2ovpworld.orgram
Busbus1(builtin)address width:32



Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments

Table 3: Platform Arguments

NameTypeDescription
kernelstringvarthe uc/OS-II image



Processor [arm.ovpworld.org/processor/armm/1.0] instance: cpu1

Processor model type: 'armm' variant 'Cortex-M3' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/armm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_armm_Cortex-M3.pdf

Description
ARMM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.

Limitations
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.

Verification
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.

Features
The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
Thumb-2 instructions are supported.
MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
Bit-band region is present. Use parameter BitBandPresent to disable it if required.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu1' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips100.0The nominal MIPS for the processor
imagefileucosiiDemoApplication.ARM_CORTEX_M3.elfThe image file to load onto the processor
semihostvendorarm.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamearmNewlibThe VLNV name of a Semihost library

Table 5: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType
variantCortex-M3enum
compatibilitygdbenum


Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.

Table 6: Memory Map ( 'cpu1' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFmemory1ram
0x100000000x10000007ledledRegister
0x200000000xFFFFFFFFmemory2ram


Net Connections to processor: 'cpu1'
There are no nets connected to this processor.


Peripheral Instances


Peripheral [ovpworld.org/peripheral/ledRegister/1.0] instance: led

Description
Simple test peripheral providing a register that may be used to toggle LED outputs.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the ArmCortexMuCOS-II Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: VMI Morph Time (VMI MT) API Reference Guide
http://www.ovpworld.org: Installation, Getting Started with OVP, and Cross-Compiling Applications

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARM Bare Metal Demos Video Presentation
http://www.ovpworld.org: OR1K Demo Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS