Information for Zynq_PS

This page provides detailed information about the xilinx.ovpworld.org Zynq_PS Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This module implements the Zynq 7000 Processing Sub-System (PS). The PS integrates two ARM Cortex-A9 MPCore application processors, memories and peripherals.

Limitations
This module provides the peripheral behavior required to boot a Linux Kernel or XtratuM hypervisor.

Some of the peripherals are register-only, non-functional models. See the individual peripheral model documentation for details.

Snoop Control Unit is not implemented, Trust Zone memory protection is not implemented

Reference
ZC702 Board user Guide UG850 (v1.5) September 4,2015 (ug850-zc702-eval-bd.pdf) and ZC706 Evaluation Board for the Zynq-7000 XC7Z045 All Programmable SoC (v1.6) March 29, 2016 (ug954-zc706-eval-bd-xc7z04-ap-soc.pdf) and Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.10) February 23, 2015 (ug585-Zynq-7000-TRM.pdf)

Description
This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

The DEVCFG provides XADC access for power monitoring.

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

This is a dummy peripheral that implements register set only

Location
The Zynq_PS virtual platform is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / module / Zynq_PS / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpuarm.ovpworld.orgarmCortex-A9MPx2
Peripheraluart0cadence.ovpworld.orguart
Peripheraluart1cadence.ovpworld.orguart
Peripheralusb0xilinx.ovpworld.orgzynq_7000-usb
Peripheralusb1xilinx.ovpworld.orgzynq_7000-usb
Peripherali2c0xilinx.ovpworld.orgzynq_7000-iic
Peripherali2c1xilinx.ovpworld.orgzynq_7000-iic
Peripheralspi0xilinx.ovpworld.orgzynq_7000-spi
Peripheralspi1xilinx.ovpworld.orgzynq_7000-spi
Peripheralcan0xilinx.ovpworld.orgzynq_7000-can
Peripheralcan1xilinx.ovpworld.orgzynq_7000-can
PeripheralGPIOxilinx.ovpworld.orgzynq_7000-gpio
Peripheraleth0xilinx.ovpworld.orgzynq_7000-gem
Peripheraleth1xilinx.ovpworld.orgzynq_7000-gem
Peripheralqspixilinx.ovpworld.orgzynq_7000-qspi
PeripheraldummySMCovpworld.orgdummyPort
PeripheraldummyUnknown1ovpworld.orgdummyPort
Peripheralsdio0xilinx.ovpworld.orgzynq_7000-sdio
Peripheralsdio1xilinx.ovpworld.orgzynq_7000-sdio
Peripheraltrustzone_securityxilinx.ovpworld.orgzynq_7000-tz_security
Peripheralslcrxilinx.ovpworld.orgzynq_7000-slcr
Peripheralttc0xilinx.ovpworld.orgzynq_7000-ttc
Peripheralttc1xilinx.ovpworld.orgzynq_7000-ttc
PeripheralDMACxilinx.ovpworld.orgzynq_7000-dmac
Peripheralswdtxilinx.ovpworld.orgzynq_7000-swdt
PeripheralDDRCxilinx.ovpworld.orgzynq_7000-ddrc
Peripheraldevcfgxilinx.ovpworld.orgzynq_7000-devcfg
PeripheraldummyAXI_HP0ovpworld.orgdummyPort
PeripheraldummyAXI_HP1ovpworld.orgdummyPort
PeripheraldummyAXI_HP2ovpworld.orgdummyPort
PeripheraldummyAXI_HP3ovpworld.orgdummyPort
PeripheralOCMxilinx.ovpworld.orgzynq_7000-ocm
PeripheraldummyeFuseovpworld.orgdummyPort
PeripheraldummyUnknown2ovpworld.orgdummyPort
Peripheraltrustzone_GPVsecurityxilinx.ovpworld.orgzynq_7000-tz_GPVsecurity
PeripheralGPV_qos301_cpuxilinx.ovpworld.orgzynq_7000-qos301
PeripheralGPV_qos301_dmacxilinx.ovpworld.orgzynq_7000-qos301
PeripheralGPV_qos301_iouxilinx.ovpworld.orgzynq_7000-qos301
Peripherall2cachearm.ovpworld.orgL2CachePL310
MemoryDDR0ovpworld.orgram
MemoryDDR1ovpworld.orgram
MemoryDDR2ovpworld.orgram
MemoryDDR3ovpworld.orgram
Memoryocmovpworld.orgram
MemoryxadcMemovpworld.orgram
BuspBus(builtin)address width:32
BusddrBus(builtin)address width:32
BusddrSBus(builtin)address width:32
BusextPortBus(builtin)address width:32
BusapbBus(builtin)address width:32
BusocmBus(builtin)address width:32
Busi2cBus(builtin)address width:16
BusxadcBus(builtin)address width:16
BridgebrPtoDDR(builtin)
BridgebrPtoDDRS(builtin)
BridgeextPorttoDDRS(builtin)
BridgeextPorttoAPB(builtin)
BridgepBustoAPB(builtin)
BridgepBustoExtPort(builtin)


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module Zynq_PS

Table 3: External Ports

Port TypePort NameInternal Connection
busportextPortextPortBus
busportextPortI2Ci2cBus
netportirqf2p0_inPirqf2p0
netportirqf2p1_inPirqf2p1
netportirqf2p2_inPirqf2p2
netportirqf2p3_inPirqf2p3
netportirqf2p4_inPirqf2p4
netportirqf2p5_inPirqf2p5
netportirqf2p6_inPirqf2p6
netportirqf2p7_inPirqf2p7
netportirqf2p8_inPirqf2p8
netportirqf2p9_inPirqf2p9
netportirqf2p10_inPirqf2p10
netportirqf2p11_inPirqf2p11
netportirqf2p12_inPirqf2p12
netportirqf2p13_inPirqf2p13
netportirqf2p14_inPirqf2p14
netportirqf2p15_inPirqf2p15
netportirqf2p16_inPirqf2p16
netportirqf2p17_inPirqf2p17
netportirqf2p18_inPirqf2p18
netportirqf2p19_inPirqf2p19
netportirqp2f0_outPcan1_spi83
netportirqp2f1_outPuart1_spi82
netportirqp2f2_outPspi1_spi81
netportirqp2f3_outPi2c1_spi80
netportirqp2f4_outPsdio1_spi79
netportirqp2f5_outPeth1wu_spi78
netportirqp2f6_outPeth1_spi77
netportirqp2f7_outPusb1_spi76
netportirqp2f8_outPcan0_spi60
netportirqp2f9_outPuart0_spi59
netportirqp2f10_outPspi0_spi58
netportirqp2f11_outPi2c0_spi57
netportirqp2f12_outPsdio0_spi56
netportirqp2f13_outPeth0wu_spi55
netportirqp2f14_outPeth0_spi54
netportirqp2f15_outPusb0_spi53
netportirqp2f16_outPgpio_spi52
netportirqp2f17_outPirqp2f17
netportirqp2f18_outPqspi_spi51
netportirqp2f19_outPsmc_spi50
netportirqp2f20_outPdmac0_spi46
netportirqp2f21_outPdmac1_spi47
netportirqp2f22_outPdmac2_spi48
netportirqp2f23_outPdmac3_spi49
netportirqp2f24_outPdmac4_spi72
netportirqp2f25_outPdmac5_spi73
netportirqp2f26_outPdmac6_spi74
netportirqp2f27_outPdmac7_spi75
netportirqp2f28_outPdmaca_spi45
netportgpio_bank0_outPgpio_bank0_out
netportgpio_bank0_inPgpio_bank0_in
netportgpio_bank1_outPgpio_bank1_out
netportgpio_bank1_inPgpio_bank1_in
netportgpio_bank2_outPgpio_bank2_out
netportgpio_bank2_oen_outPgpio_bank2_oen_out
netportgpio_bank2_inPgpio_bank2_in
netportgpio_bank3_outPgpio_bank3_out
netportgpio_bank3_oen_outPgpio_bank3_oen_out
netportgpio_bank3_inPgpio_bank3_in



Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A9MPx2' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A9MPx2.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Core Features
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.

Memory System
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
VMSA secure and non-secure address translation is implemented.

Advanced SIMD and Floating-Point Features
SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Interrupt Controller
GIC block is implemented (GICv1, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register ICDDCR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register ICDDCR can be observed by monitoring address 0x80001000

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter enableSystemMonitorBus is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter enableSystemBus is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mipsarmmipsThe nominal MIPS for the processor

Table 5: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantCortex-A9MPx2enum
compatibilityISAenum
UAL1boolean
override_CBAR0xf8f00000Uns32
override_MIDR0x413fc090Uns32


Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 6: Memory Map ( 'cpu' / 'pBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFbrPtoDDRbridge
remappableremappableslcrzynq_7000-slcr
0x1000000x3FFFFFFFbrPtoDDRSbridge
0x400000000xBFFFFFFFpBustoExtPortbridge
0xE00000000xE0101FFFpBustoAPBbridge
0xE02000000xE020001Ftrustzone_securityzynq_7000-tz_security
0xF80000000xF8000BFFslcrzynq_7000-slcr
0xF80010000xF8001FFFttc0zynq_7000-ttc
0xF80020000xF8002FFFttc1zynq_7000-ttc
0xF80030000xF8003FFFDMACzynq_7000-dmac
0xF80040000xF8004FFFDMACzynq_7000-dmac
0xF80050000xF8005FFFswdtzynq_7000-swdt
0xF80060000xF8006FFFDDRCzynq_7000-ddrc
0xF80070000xF8007FFFdevcfgzynq_7000-devcfg
0xF80080000xF8008FFFdummyAXI_HP0dummyPort
0xF80090000xF8009FFFdummyAXI_HP1dummyPort
0xF800A0000xF800AFFFdummyAXI_HP2dummyPort
0xF800B0000xF800BFFFdummyAXI_HP3dummyPort
0xF800C0000xF800CFFFOCMram
0xF800D0000xF800DFFFdummyeFusedummyPort
0xF800E0000xF800EFFFdummyUnknown2dummyPort
0xF89000000xF890003Ftrustzone_GPVsecurityzynq_7000-tz_GPVsecurity
0xF89460000xF8946FFFGPV_qos301_cpuzynq_7000-qos301
0xF89470000xF8947FFFGPV_qos301_dmaczynq_7000-qos301
0xF89480000xF8948FFFGPV_qos301_iouzynq_7000-qos301
0xF8F020000xF8F02FFFl2cacheL2CachePL310

Table 7: Bridged Memory Map ( 'cpu' / 'brPtoDDR' / 'ddrBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFDDR0ram
0x400000x7FFFFDDR1ram
0x800000xFFFFFDDR2ram

Table 8: Bridged Memory Map ( 'cpu' / 'brPtoDDRS' / 'ddrSBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1000000x3FFFFFFFDDR3ram

Table 9: Bridged Memory Map ( 'cpu' / 'pBustoExtPort' / 'extPortBus' [width: 32] )

Lo AddressHi AddressInstanceComponent

Table 10: Bridged Memory Map ( 'cpu' / 'pBustoAPB' / 'apbBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0xE00000000xE0000FFFuart0uart
0xE00010000xE0001FFFuart1uart
0xE00020000xE0002FFFusb0zynq_7000-usb
0xE00030000xE0003FFFusb1zynq_7000-usb
0xE00040000xE0004FFFi2c0zynq_7000-iic
0xE00050000xE0005FFFi2c1zynq_7000-iic
0xE00060000xE0006FFFspi0zynq_7000-spi
0xE00070000xE0007FFFspi1zynq_7000-spi
0xE00080000xE0008FFFcan0zynq_7000-can
0xE00090000xE0009FFFcan1zynq_7000-can
0xE000A0000xE000AFFFGPIOzynq_7000-gpio
0xE000B0000xE000BFFFeth0zynq_7000-gem
0xE000C0000xE000CFFFeth1zynq_7000-gem
0xE000D0000xE000DFFFqspizynq_7000-qspi
0xE000E0000xE000EFFFdummySMCdummyPort
0xE000F0000xE000FFFFdummyUnknown1dummyPort
0xE01000000xE0100FFFsdio0zynq_7000-sdio
0xE01010000xE0101FFFsdio1zynq_7000-sdio


Net Connections to processor: 'cpu'

Table 11: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
SPI34l2cache_spi34l2cacheL2CachePL310
SPI41swdt_spi41swdtzynq_7000-swdt
SPI42ttc0_spi42ttc0zynq_7000-ttc
SPI43ttc0_spi43ttc0zynq_7000-ttc
SPI44ttc0_spi44ttc0zynq_7000-ttc
SPI45dmaca_spi45unknown
SPI45dmaca_spi45DMACzynq_7000-dmac
SPI46dmac0_spi46unknown
SPI47dmac1_spi47unknown
SPI48dmac2_spi48unknown
SPI49dmac3_spi49unknown
SPI50smc_spi50unknown
SPI51qspi_spi51unknown
SPI52gpio_spi52unknown
SPI53usb0_spi53unknown
SPI54eth0_spi54unknown
SPI54eth0_spi54eth0zynq_7000-gem
SPI55eth0wu_spi55unknown
SPI56sdio0_spi56unknown
SPI56sdio0_spi56sdio0zynq_7000-sdio
SPI57i2c0_spi57unknown
SPI57i2c0_spi57i2c0zynq_7000-iic
SPI58spi0_spi58unknown
SPI58spi0_spi58spi0zynq_7000-spi
SPI59uart0_spi59unknown
SPI59uart0_spi59uart0uart
SPI60can0_spi60unknown
SPI60can0_spi60can0zynq_7000-can
SPI69ttc1_spi69ttc1zynq_7000-ttc
SPI70ttc1_spi70ttc1zynq_7000-ttc
SPI71ttc1_spi71ttc1zynq_7000-ttc
SPI72dmac4_spi72unknown
SPI73dmac5_spi73unknown
SPI74dmac6_spi74unknown
SPI75dmac7_spi75unknown
SPI76usb1_spi76unknown
SPI77eth1_spi77unknown
SPI77eth1_spi77eth1zynq_7000-gem
SPI78eth1wu_spi78unknown
SPI79sdio1_spi79unknown
SPI79sdio1_spi79sdio1zynq_7000-sdio
SPI80i2c1_spi80unknown
SPI80i2c1_spi80i2c1zynq_7000-iic
SPI81spi1_spi81unknown
SPI81spi1_spi81spi1zynq_7000-spi
SPI82uart1_spi82unknown
SPI82uart1_spi82uart1uart
SPI83can1_spi83unknown
SPI83can1_spi83can1zynq_7000-can
SPI61irqf2p0unknown
SPI62irqf2p1unknown
SPI63irqf2p2unknown
SPI64irqf2p3unknown
SPI65irqf2p4unknown
SPI66irqf2p5unknown
SPI67irqf2p6unknown
SPI68irqf2p7unknown
SPI84irqf2p8unknown
SPI85irqf2p9unknown
SPI86irqf2p10unknown
SPI87irqf2p11unknown
SPI88irqf2p12unknown
SPI89irqf2p13unknown
SPI90irqf2p14unknown
SPI91irqf2p15unknown
irq_CPU0irqf2p16unknown
fiq_CPU0irqf2p17unknown
irq_CPU1irqf2p18unknown
fiq_CPU1irqf2p19unknown
reset_CPU0reset_A9_CPU0slcrzynq_7000-slcr
reset_CPU1reset_A9_CPU1slcrzynq_7000-slcr



Peripheral Instances


Peripheral [cadence.ovpworld.org/peripheral/uart/1.0] instance: uart0

Description
Cadence UART (Xilinx Zync Platform)

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the Cadence UART (uartps) as used on the Xilinx Zync devices.
It has basic functionality to support Linux boot on the Xilinx Zync platform.
There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

Table 12: Configuration options (attributes) set for instance 'uart0'

AttributesValue
outfileuart0.log
finishOnDisconnect1
console1



Peripheral [cadence.ovpworld.org/peripheral/uart/1.0] instance: uart1

Description
Cadence UART (Xilinx Zync Platform)

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the Cadence UART (uartps) as used on the Xilinx Zync devices.
It has basic functionality to support Linux boot on the Xilinx Zync platform.
There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

Table 13: Configuration options (attributes) set for instance 'uart1'

AttributesValue
outfileuart1.log
finishOnDisconnect1
console1



Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-usb/1.0] instance: usb0

Description
Zynq 7000 USB Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-usb/1.0] instance: usb1

Description
Zynq 7000 USB Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-iic/1.0] instance: i2c0

Description
Zynq 7000 I2C Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-iic/1.0] instance: i2c1

Description
Zynq 7000 I2C Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-spi/1.0] instance: spi0

Description
Zynq 7000 SPI Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-spi/1.0] instance: spi1

Description
Zynq 7000 SPI Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-can/1.0] instance: can0

Description
Zynq 7000 CAN Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-can/1.0] instance: can1

Description
Zynq 7000 CAN Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-gpio/1.0] instance: GPIO

Description
Zynq 7000 Platform GPIO Registers (gpio)
Included is the visualization of LED and SW connectivity for the ZC702/ZC706 devices.

Licensing
Open Source Apache 2.0

Limitations
This model implements only the registers for generation of input or output data values.
No interrupt generation is currently included in the model.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-gem/1.0] instance: eth0

Description
Model of Xilinx Zynq 7000 Gigabit Ethernet Controller (GEM). For further details please consult README-EMAC.txt
Basic network Tx/Rx functionality tested using Xilinx Linux Kernel using wget and other similar tools
Tested with Xilinx SDK Example driver.

Licensing
Open Source Apache 2.0

Limitations
This is a preliminary model.
Does not implement: VLAN, pause frames, filtering or timestamps.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-gem/1.0] instance: eth1

Description
Model of Xilinx Zynq 7000 Gigabit Ethernet Controller (GEM). For further details please consult README-EMAC.txt
Basic network Tx/Rx functionality tested using Xilinx Linux Kernel using wget and other similar tools
Tested with Xilinx SDK Example driver.

Licensing
Open Source Apache 2.0

Limitations
This is a preliminary model.
Does not implement: VLAN, pause frames, filtering or timestamps.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-qspi/1.0] instance: qspi

Description
Zynq 7000 Quad-SPI Registers and incorporates Flash Memory for Zync zc702/zc706 boards

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but not all flash memory accesses are supported.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummySMC

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyUnknown1

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-sdio/1.0] instance: sdio0

Description
Zynq 7000 SD/SDIO Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-sdio/1.0] instance: sdio1

Description
Zynq 7000 SD/SDIO Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-tz_security/1.0] instance: trustzone_security

Description
Zynq 7000 Trust Zone Security Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf) and ug1019-zynq-trustzone

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-slcr/1.0] instance: slcr

Description
Zynq 7000 Platform System Level Control Registers (SLCR)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. Only behavior required for processor reset control is included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

Table 14: Configuration options (attributes) set for instance 'slcr'

AttributesValue
deviceid0x11
psclockpsclock
armmipsarmmips



Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-ttc/1.0] instance: ttc0

Description
Zynq 7000 Triple Timer Counter Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers and basic behavior. It is not yet completed.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-ttc/1.0] instance: ttc1

Description
Zynq 7000 Triple Timer Counter Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers and basic behavior. It is not yet completed.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-dmac/1.0] instance: DMAC

Description
Zynq 7000 Platform DMA Controller (DMAC)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-swdt/1.0] instance: swdt

Description
Zynq 7000 System Watchdog Timer Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-ddrc/1.0] instance: DDRC

Description
Zynq 7000 Platform DDR Memory Controller (DDRC)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-devcfg/1.0] instance: devcfg

Description
Zynq 7000 Platform Device Configuration Registers (devcfg)

Licensing
Open Source Apache 2.0

Limitations
This is mainly a register only interface model. It provides behavior to access the power rails using the XADC interface. The power rail data is provided by values stored in memory which can be updated externally. It provides the ability to lock and un-lock registers.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyAXI_HP0

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyAXI_HP1

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyAXI_HP2

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyAXI_HP3

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-ocm/1.0] instance: OCM

Description
Zynq 7000 Platform On Chip Memory Controller Registers (OCM)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyeFuse

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: dummyUnknown2

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-tz_GPVsecurity/1.0] instance: trustzone_GPVsecurity

Description
Zynq 7000 Trust Zone GPV Security Registers

Licensing
Open Source Apache 2.0

Limitations
This model implements the set of registers but no behavior.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf) and ug1019-zynq-trustzone

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-qos301/1.0] instance: GPV_qos301_cpu

Description
Zynq 7000 Platform Interconnect QoS (qos301)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-qos301/1.0] instance: GPV_qos301_dmac

Description
Zynq 7000 Platform Interconnect QoS (qos301)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/zynq_7000-qos301/1.0] instance: GPV_qos301_iou

Description
Zynq 7000 Platform Interconnect QoS (qos301)

Licensing
Open Source Apache 2.0

Limitations
This model implements the full set of registers. There is no behavior included.

Reference
Zynq-7000 TRM (ug858-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/L2CachePL310/1.0] instance: l2cache

Description
ARM PL310 L2 Cache Control Registers

Licensing
Open Source Apache 2.0

Limitations
Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference
ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual (ARM DDI 0246)

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the Zynq_PS Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging Applications with INSIGHT running on OVP platforms
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms

Two Videos on these models (from other sites)
http://www.ovpworld.org: PowerPC Bare Metal Video Presentation
http://www.ovpworld.org: ARM Bare Metal Demos Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS