What Tools do you need to build and use Virtual Platforms

Execution of the virtual platform – Simulation

If you are using an existing Imperas / OVP virtual platform, then all you need is an Imperas or OVP simulator.

The simulator utilizes Just-In-Time code morphing to enable particularly high-performance execution speed on standard x86 desktop computers. By generating execution code on the fly, and combining this with other Imperas proprietary optimization schemes, the simulation performance that is achieved allows embedded code to be executed, often, faster than real time. Very large numbers of tests may be executed on embedded code within reasonable timescales, allowing product quality to be increased.

Building or extending virtual platforms

To build virtual platforms for use with the Imperas or OVP simulators you can write the models in C using the appropriate OVP API. Alternatively you can use the Imperas iGen product.

iGen is a productivity tool from Imperas that is a model framework generation system. iGen takes the laborious and error-prone task of constructing the various hardware model and software element files required for a typical model or platform, and automates this process.

iGen takes as input a simple TCL specification that includes device internals such as registers and memories, port information,  component descriptors, and other elements.

iGen builds three sets of model items, C code model files, user editable templates, and XML descriptions. These include model frameworks with registers, function calls, memory map, and other items, including matching XML information. It ensures that all component parts of the model are well-structured using best practices, and are consistent throughout the files, thus eliminating a common source of errors.

iGen presents to the developer a set of function calls and model elements that simply need to be filled in with required behavior, thereby reducing the set up overhead of a new model significantly. iGen also creates code in the model to provide very efficient run time tracing and diagnostics.

Embedded Software Development and Debugging

The Imperas simulators can operate with GNU’s GDB debugger, with or without the Eclipse IDE. The Imperas Multicore Software Development Kit (M*SDK) may be used which allows an extensive range of options for the verification, analysis and profiling of designs. The M*SDK also contains a powerful, three-dimensional debugger (temporal, spatial and abstract) that is CPU- and OS-aware and which adds to GDB-like functionality a series of options to target complex homogeneous/heterogeneous multicore platform debug.

 Advanced tools – parallel simulation

While OVPsim and the Imperas simulator products are very fast, running at 100s of millions of instructions per second, additional speed can be achieved for virtual platforms which include multiple processor instances, multicore processors and processors that support hardware multithreading.  The Imperas QuantumLeap parallel simulation accelerator is an add-on to the Imperas simulator products.  Its MultiProcessor target on MultiProcessor host technology enables the simulator to take advantage of the multiple x86 cores in the host machine.  This can result, for example, in an increase in performance of 2.25x for a 4-core virtual platform with SMP architecture running on a 4-core host PC.


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS