Information for BareMetalMipsDual

This page provides detailed information about the mips.ovpworld.org BareMetalMipsDual Virtual Platform / Virtual Prototype.

Description
Bare Metal Platform for a MIPS32 Processor (default 74Kc). The bare metal platform instantiates two MIPS32 processor instances. The processor operates using big endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The ICM platform can be passed any application compiled to a MIPS elf format. The same application executes on each processor. There is no sharing of data. It may also be passed a new variant to be used (default 74Kc) ./platform.OS.exe --program application.CROSS.elf [--variant ]

Licensing
Open Source Apache 2.0

Limitations
BareMetal platform for execution of MIPS MIPS32 binary files compiled with CodeSourcery CrossCompiler toolchain.

Location
The BareMetalMipsDual virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / platform / BareMetalMipsDual / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpu0mips.ovpworld.orgmips3274Kc
Processorcpu1mips.ovpworld.orgmips3274Kc
Memorymemory0ovpworld.orgram
Memorymemory1ovpworld.orgram
Busbus0(builtin)address width:32
Busbus1(builtin)address width:32


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Command Line Control of the Platform

Built-in Arguments

Table 3: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.


Processor [mips.ovpworld.org/processor/mips32/1.0] instance: cpu0

Processor model type: 'mips32' variant '74Kc' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_74Kc.pdf

Description
MIPS32 Configurable Processor Model

Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs

Features
MIPS32 Instruction set implemented
MMU Type: Standard TLB
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
DSP ASE Rev 2 implemented

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu0' Parameters (Configurations)

ParameterValueDescription
endianbigSelect processor endian (big or little)
mips100The nominal MIPS for the processor
semihostvendormips.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamemips32NewlibThe VLNV name of a Semihost library

Table 5: Processor Instance 'cpu0' Parameters (Attributes)

Parameter NameValueType
variant74Kcenum


Memory Map for processor 'cpu0' bus: 'bus0'
Processor instance 'cpu0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'cpu0' is connected to bus 'bus0' using master port 'DATA'.

Table 6: Memory Map ( 'cpu0' / 'bus0' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemory0ram


Net Connections to processor: 'cpu0'
There are no nets connected to this processor.


Processor [mips.ovpworld.org/processor/mips32/1.0] instance: cpu1

Processor model type: 'mips32' variant '74Kc' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_74Kc.pdf

Description
MIPS32 Configurable Processor Model

Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs

Features
MIPS32 Instruction set implemented
MMU Type: Standard TLB
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
DSP ASE Rev 2 implemented

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 7: Processor Instance 'cpu1' Parameters (Configurations)

ParameterValueDescription
endianbigSelect processor endian (big or little)
mips100The nominal MIPS for the processor
semihostvendormips.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamemips32NewlibThe VLNV name of a Semihost library

Table 8: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType
variant74Kcenum


Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.

Table 9: Memory Map ( 'cpu1' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemory1ram


Net Connections to processor: 'cpu1'
There are no nets connected to this processor.


Other Sites/Pages with similar information

Information on the BareMetalMipsDual Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Creating & Using Platforms and Models in C++ with OP API
http://www.ovpworld.org: DEPRECATED: OVPsim Simulation Guide - Creating, Modifying, compiling and simulating platforms using

Two Videos on these models (from other sites)
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS