Information for BareMetalMipsSingle

This page provides detailed information about the mips.ovpworld.org BareMetalMipsSingle Virtual Platform / Virtual Prototype.

Description
Bare Metal Platform for a MIPS Processor. The bare metal platform instantiates a single MIPS processor instance, using big endian data ordering. It creates memory across the full address space 0x00000000 to 0xffffffff. The platform can be passed any application compiled to a MIPS elf format as the argument, select the variant of processor that should be used platform.OS.exe application.CROSS.elf 'port number for connecting GDB' Where OS is Linux or Windows and CROSS is the CrossCompiler toolchain used A further option may be added to the command line to specify the port to attach the debugger.

Licensing
Open Source Apache 2.0

Limitations
BareMetal platform for execution of MIPS MIPS32 binary files compiled with CodeSourcery CrossCompiler toolchain.

Location
The BareMetalMipsSingle virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / platform / BareMetalMipsSingle / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpu0mips.ovpworld.orgmips32_r1r5
Memorymemoryovpworld.orgram
Busbus1(builtin)address width:32



Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.


Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: cpu0

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu0' Parameters (Configurations)

ParameterValueDescription
endianbigSelect processor endian (big or little)
mips100The nominal MIPS for the processor
semihostvendormips.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostlibrarysemihostingThe VLNV library name of a Semihost library
semihostnamemips32NewlibThe VLNV name of a Semihost library
semihostversion1.0The VLNV version number of a Semihost library


Memory Map for processor 'cpu0' bus: 'bus1'
Processor instance 'cpu0' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu0' is connected to bus 'bus1' using master port 'DATA'.

Table 4: Memory Map ( 'cpu0' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemoryram


Net Connections to processor: 'cpu0'
There are no nets connected to this processor.


Other Sites/Pages with similar information

Information on the BareMetalMipsSingle Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Visualization used in Virtual Platforms.
http://www.ovpworld.org: Creating Instruction Accurate Processor models using the VMI API

Two Videos on these models (from other sites)
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS