Information for HeteroArmNucleusMIPSLinux

This page provides detailed information about the imperas.ovpworld.org HeteroArmNucleusMIPSLinux Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This heterogeneous platform combines MIPS Malta and ARM Integrator platforms.

MIPS Malta executes a Linux Kernel Operating System.

ARM Integrator executes the Nucleus Operating System.

Limitations
Peripherals are modeled only to the extent required to boot and run Operating Systems.

Reference
OVP Heterogeneous platforms. MIPS Malta and ARM IntgratorCP reference guides.

Location
The HeteroArmNucleusMIPSLinux virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / platform / HeteroArmNucleusMIPSLinux / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processormipsle1mips.ovpworld.orgmips3234Kf
ProcessorarmSub1arm1arm.ovpworld.orgarmARM920T
PeripheralCore_Board_SDRAM_promInitmips.ovpworld.orgSmartLoaderLinux
PeripheralsysControlmarvell.ovpworld.orgGT6412x
PeripheralPIIX4intel.ovpworld.org82371EB
PeripheralPIIX4-IDEintel.ovpworld.orgPciIDE
PeripheralPCI_USBintel.ovpworld.orgPciUSB
PeripheralPCI_PMintel.ovpworld.orgPciPM
PeripheralPCI_NETamd.ovpworld.org79C970
PeripheralintCtrlMasterintel.ovpworld.org8259A
PeripheralintCtrlSlaveintel.ovpworld.org8259A
Peripheralvgacirrus.ovpworld.orgGD5446
PeripheralPs2Controlintel.ovpworld.orgPs2Control
Peripheralmpitintel.ovpworld.org8253
Peripheralmrtcmotorola.ovpworld.orgMC146818
PeripheraluartTTY0national.ovpworld.org16550
PeripheraluartTTY1national.ovpworld.org16550
PeripheraluartCBUSmips.ovpworld.org16450C
Peripheralfd0intel.ovpworld.org82077AA
PeripheralmaltaFpgamips.ovpworld.orgMaltaFPGA
PeripheralarmSub1cmarm.ovpworld.orgCoreModule9x6
PeripheralarmSub1pic1arm.ovpworld.orgIntICP
PeripheralarmSub1pic2arm.ovpworld.orgIntICP
PeripheralarmSub1pitarm.ovpworld.orgIcpCounterTimer
PeripheralarmSub1icparm.ovpworld.orgIcpControl
PeripheralarmSub1ld1arm.ovpworld.orgDebugLedAndDipSwitch
PeripheralarmSub1kb1arm.ovpworld.orgKbPL050
PeripheralarmSub1ms1arm.ovpworld.orgKbPL050
PeripheralarmSub1rtcarm.ovpworld.orgRtcPL031
PeripheralarmSub1uart1arm.ovpworld.orgUartPL011
PeripheralarmSub1uart2arm.ovpworld.orgUartPL011
PeripheralarmSub1mmciarm.ovpworld.orgMmciPL181
PeripheralarmSub1lcdarm.ovpworld.orgLcdPL110
PeripheralarmSub1smartLoaderarm.ovpworld.orgSmartLoaderArmLinux
MemoryCore_Board_SDRAMovpworld.orgram
MemoryMonitor_Flashovpworld.orgram
MemoryarmSub1ram1ovpworld.orgram
MemoryarmSub1ambaDummyovpworld.orgram
MemorysharedRAMovpworld.orgram
BusbusmipsMain(builtin)address width:32
BusPCIconfigBusmipsMain(builtin)address width:16
BusPCIackBusmipsMain(builtin)address width:1
BuscascadeBusmipsMain(builtin)address width:3
BusflashBus(builtin)address width:32
BusbusarmSub1(builtin)address width:32
BusbusShared(builtin)address width:32
Bridgemap(builtin)
Bridgeremap1(builtin)
Bridgeremap2(builtin)
BridgearmSub1ram1Bridge(builtin)
BridgebusBridgeM1(builtin)
BridgebusBridgeA1(builtin)



Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments

Table 3: Platform Arguments

NameTypeDescription
uartconsoleboolvaropen a console terminal on the ARM IntegratorCP UART
uartportuns64varset the base port number to open on the ARM IntegratorCP UART
nographicsboolvardisable the MIPS Malta graphics window



Processor [mips.ovpworld.org/processor/mips32/1.0] instance: mipsle1

Processor model type: 'mips32' variant '34Kf' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_34Kf.pdf

Description
MIPS32 Configurable Processor Model

Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs

Features
MIPS32 Instruction set implemented
MMU Type: Standard TLB
FPU implemented
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
MT ASE implemented
DSP ASE implemented

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'mipsle1' it has been instanced with the following parameters:

Table 4: Processor Instance 'mipsle1' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips100The nominal MIPS for the processor
imagefilemips.vmlinuxThe image file to load onto the processor

Table 5: Processor Instance 'mipsle1' Parameters (Attributes)

Parameter NameValueType
variant34Kfenum
vectoredinterrupt0bool
config1MMUSizeM163uns32


Memory Map for processor 'mipsle1' bus: 'busmipsMain'
Processor instance 'mipsle1' is connected to bus 'busmipsMain' using master port 'INSTRUCTION'.

Processor instance 'mipsle1' is connected to bus 'busmipsMain' using master port 'DATA'.

Table 6: Memory Map ( 'mipsle1' / 'busmipsMain' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x7FFFFFFCore_Board_SDRAMram
remappableremappablePCI_NET79C970
remappableremappablePCI_PMPciPM
remappableremappablePCI_USBPciUSB
remappableremappablePIIX4-IDEPciIDE
remappableremappablesysControlGT6412x
remappableremappablevgaGD5446
0x80000000x800FFFFbusBridgeM1bridge
0x180000200x18000021intCtrlMaster8259A
0x180000400x18000043mpit8253
0x180000600x18000067Ps2ControlPs2Control
0x180000700x18000071mrtcMC146818
0x180000A00x180000A1intCtrlSlave8259A
0x180002F80x180002FFuartTTY116550
0x180003B00x180003DFvgaGD5446
0x180003F00x180003F7fd082077AA
0x180003F80x180003FFuartTTY016550
0x180004D00x180004D0intCtrlMaster8259A
0x180004D10x180004D1intCtrlSlave8259A
0x1E0000000x1E3FFFFFmapbridge
0x1F0000000x1F0008FFmaltaFpgaMaltaFPGA
0x1F0009000x1F00093FuartCBUS16450C
0x1F000A000x1F000FFFmaltaFpgaMaltaFPGA
0x1FC000000x1FC0000Fremap1bridge
0x1FC000100x1FC00013Core_Board_SDRAM_promInitSmartLoaderLinux
0x1FC000140x1FFFFFFFremap2bridge

Table 7: Bridged Memory Map ( 'mipsle1' / 'busBridgeM1' / 'busShared' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFsharedRAMram

Table 8: Bridged Memory Map ( 'mipsle1' / 'map' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram

Table 9: Bridged Memory Map ( 'mipsle1' / 'remap1' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram

Table 10: Bridged Memory Map ( 'mipsle1' / 'remap2' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram


Net Connections to processor: 'mipsle1'

Table 11: Processor Net Connections ( 'mipsle1' )

Net PortNetInstanceComponent
hwint0i8259IntintCtrlMaster8259A



Processor [arm.ovpworld.org/processor/arm/1.0] instance: armSub1arm1

Processor model type: 'arm' variant 'ARM920T' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_ARM920T.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
Models have been extensively tested by Imperas. ARM9 models have been successfully used by customers to simulate Linux and Nucleus on ArmIntegrator virtual platforms.

Core Features
Thumb instructions are supported.

Memory System
FCSE extension is implemented.
VMSA address translation is implemented.

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter enableSystemMonitorBus is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter enableSystemBus is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'armSub1arm1' it has been instanced with the following parameters:

Table 12: Processor Instance 'armSub1arm1' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips200.0The nominal MIPS for the processor
imagefilearm.plus_demo.outThe image file to load onto the processor

Table 13: Processor Instance 'armSub1arm1' Parameters (Attributes)

Parameter NameValueType
variantARM920Tenum
compatibilityISAenum
showHiddenRegs0bool


Memory Map for processor 'armSub1arm1' bus: 'busarmSub1'
Processor instance 'armSub1arm1' is connected to bus 'busarmSub1' using master port 'INSTRUCTION'.

Processor instance 'armSub1arm1' is connected to bus 'busarmSub1' using master port 'DATA'.

Table 14: Memory Map ( 'armSub1arm1' / 'busarmSub1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x7FFFFFFarmSub1ram1Bridgebridge
remappableremappablearmSub1lcdLcdPL110
0xA0000000xA00FFFFbusBridgeA1bridge
0x100000000x10000FFFarmSub1cmCoreModule9x6
0x130000000x13000FFFarmSub1pitIcpCounterTimer
0x140000000x14000FFFarmSub1pic1IntICP
0x150000000x15000FFFarmSub1rtcRtcPL031
0x160000000x16000FFFarmSub1uart1UartPL011
0x170000000x17000FFFarmSub1uart2UartPL011
0x180000000x18000FFFarmSub1kb1KbPL050
0x190000000x19000FFFarmSub1ms1KbPL050
0x1A0000000x1A000FFFarmSub1ld1DebugLedAndDipSwitch
0x1C0000000x1C000FFFarmSub1mmciMmciPL181
0x1D0000000x1D000FFFarmSub1ambaDummyram
0x800000000x87FFFFFFarmSub1ram1ram
0xC00000000xC0000FFFarmSub1lcdLcdPL110
0xCA0000000xCA000FFFarmSub1pic2IntICP
0xCB0000000xCB00000FarmSub1icpIcpControl

Table 15: Bridged Memory Map ( 'armSub1arm1' / 'armSub1ram1Bridge' / 'busarmSub1' [width: 32] )

Lo AddressHi AddressInstanceComponent
remappableremappablearmSub1lcdLcdPL110
0x800000000x87FFFFFFarmSub1ram1ram

Table 16: Bridged Memory Map ( 'armSub1arm1' / 'busBridgeA1' / 'busShared' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFsharedRAMram


Net Connections to processor: 'armSub1arm1'

Table 17: Processor Net Connections ( 'armSub1arm1' )

Net PortNetInstanceComponent
irqarmSub1irqarmSub1pic1IntICP
fiqarmSub1fiqarmSub1pic1IntICP



Peripheral Instances


Peripheral [mips.ovpworld.org/peripheral/SmartLoaderLinux/1.0] instance: Core_Board_SDRAM_promInit

Licensing
Open Source Apache 2.0

Description
Smart peripheral creates memory initialisation for a MIPS32 based Linux kernel boot. Performs the generation of boot code at the reset vector (virtual address 0xbfc00000) of the MIPS32 processor. Loads both the linux kernel and initial ramdisk into memory and patches the boot code to jump to the kernel start. Initialises the MIPS32 registers and Linux command line.

Reference
MIPS Malta User Manual. MIPS Boot code reference.

Limitations
None

Table 18: Configuration options (attributes) set for instance 'Core_Board_SDRAM_promInit'

AttributesValue
kernelmips.vmlinux
boardid0x00000420
initrdmips.initrd.gz
commandconsole=tty0



Peripheral [marvell.ovpworld.org/peripheral/GT6412x/1.0] instance: sysControl

Licensing
Open Source Apache 2.0

Description
GT64120 System Controller.
Diagnostic levels:
PCI_SLAVE 0x03
PCI_CONFIG_MASTER 0x04
PCI_EMPTY 0x08
INT_ACK 0x10
MAIN_BUS 0x20
INFO 0x40

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
GT64121A System Controller for RC4650/4700/5000 and RM526X/527X/7000 CPUs Datasheet Revision 1.0 MAR 14, 2000

There are no configuration options set for this peripheral instance.


Peripheral [intel.ovpworld.org/peripheral/82371EB/1.0] instance: PIIX4

Licensing
Open Source Apache 2.0

Description
PIIX4 PCI configuration controller.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 19: Configuration options (attributes) set for instance 'PIIX4'

AttributesValue
PCIslot10



Peripheral [intel.ovpworld.org/peripheral/PciIDE/1.0] instance: PIIX4-IDE

Licensing
Open Source Apache 2.0

Description
PCI:IDE interface. This forms part of the 82371 PIIX4 chip. It implements 4 IDE interfaces and 2 DMA controllers.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 20: Configuration options (attributes) set for instance 'PIIX4-IDE'

AttributesValue
PCIslot10
PCIfunction1
Drive0Namemipsel_hda
Drive1Namemipsel_hdb
Drive2Namemipsel_cd



Peripheral [intel.ovpworld.org/peripheral/PciUSB/1.0] instance: PCI_USB

Licensing
Open Source Apache 2.0

Description
PCI USB Interface

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 21: Configuration options (attributes) set for instance 'PCI_USB'

AttributesValue
PCIslot10
PCIfunction2



Peripheral [intel.ovpworld.org/peripheral/PciPM/1.0] instance: PCI_PM

Licensing
Open Source Apache 2.0

Description
PCI Power Manager.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 22: Configuration options (attributes) set for instance 'PCI_PM'

AttributesValue
PCIslot10
PCIfunction3



Peripheral [amd.ovpworld.org/peripheral/79C970/1.0] instance: PCI_NET

Licensing
Open Source Apache 2.0

Description
Implements part of the AMD AM79C97xx series Ethernet devices.
diagnosticlevel: bits 0:1 give levels for the network hardware. bits 2:3 give levels for the user:mode SLIRP interface.

Limitations
Sufficient behavior is implemented to Boot MIPS Linux and support TCP/IP protocol access.
This model implementation does not use the current BHM API features that support Ethernet interfaces. Please examine the source of the models with VLNV smsc.ovpworld.org/peripheral/LAN91*/1.0 for ones using the current BHM API implementation.

Reference
AMD Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Datasheet

Table 23: Configuration options (attributes) set for instance 'PCI_NET'

AttributesValue
PCIslot11
PCIfunction0
pollDelay1000



Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlMaster

Licensing
Open Source Apache 2.0

Description
Intel 8259A Programmable Interrupt Controller (PIT).

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.

Table 24: Configuration options (attributes) set for instance 'intCtrlMaster'

AttributesValue
spenmaster



Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlSlave

Licensing
Open Source Apache 2.0

Description
Intel 8259A Programmable Interrupt Controller (PIT).

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.

Table 25: Configuration options (attributes) set for instance 'intCtrlSlave'

AttributesValue
spenslave



Peripheral [cirrus.ovpworld.org/peripheral/GD5446/1.0] instance: vga

Licensing
Open Source Apache 2.0

Description
Cirrus CL GD5446 VGA controller.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. The VGA peripheral utilises memory mapping. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.

Reference
CL-GD5446 Preliminary Databook, Version 2.0, November 1996

Table 26: Configuration options (attributes) set for instance 'vga'

AttributesValue
scanDelay50000
PCIslot18
titleImperas MIPS32 Malta
noGraphics



Peripheral [intel.ovpworld.org/peripheral/Ps2Control/1.0] instance: Ps2Control

Licensing
Open Source Apache 2.0

Description
PS2 Keyboard/Mouse Controller.

Limitations
This is a preliminary model with sufficient functionality to enable Linux to Boot on the MIPS:MALTA platform. Mouse functions are currently turned off.

Reference
SMsC FDC37M817 Super I/O Controller Datasheet

Table 27: Configuration options (attributes) set for instance 'Ps2Control'

AttributesValue
pollPeriod5000
grabDisable1



Peripheral [intel.ovpworld.org/peripheral/8253/1.0] instance: mpit

Description
Intel 8253 Programmable Interval Timer (PIT)

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. Not all modes are supported.

Licensing
Open Source Apache 2.0

Reference
Intel 8253 Datasheet. MIPS Malta Platform Reference Guide.

There are no configuration options set for this peripheral instance.


Peripheral [motorola.ovpworld.org/peripheral/MC146818/1.0] instance: mrtc

Licensing
Open Source Apache 2.0

Description
MC146818 Real:time clock.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Motorola MC146818AS Datasheet

There are no configuration options set for this peripheral instance.


Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY0

Licensing
Open Source Apache 2.0

Description
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY1

Licensing
Open Source Apache 2.0

Description
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [mips.ovpworld.org/peripheral/16450C/1.0] instance: uartCBUS

Licensing
Open Source Apache 2.0

Description
Model of 16550/16450 UART.
Special version with register addresses for MIPS MALTA C-BUS.
Connects to a bus by a slave port and optionally to a processor by an interrupt signal.
The serial input/output ports are modelled by socket connection which must be attached to a process outside the simulation environment.
Note that on start:up, the UART model will block the simulator, pending a connection to the socket.

Limitations
No modelling of baud:rate.
No modem support (DTR etc).
No support for parity.
No means to simulate errors.

Reference
MIPS Malta Datasheet

There are no configuration options set for this peripheral instance.


Peripheral [intel.ovpworld.org/peripheral/82077AA/1.0] instance: fd0

Licensing
Open Source Apache 2.0

Description
Dummy Floppy Disc Controller.

Limitations
Register stubs only.

Reference
http://www.buchty.net/casio/files/82077.pdf http://www.alldatasheet.com/datesheet-pdf/pdf/167793/INTEL/82077AA.html

There are no configuration options set for this peripheral instance.


Peripheral [mips.ovpworld.org/peripheral/MaltaFPGA/1.0] instance: maltaFpga

Licensing
Open Source Apache 2.0

Description
MIPS MALTA FPGA. Drives Development board functions.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
MIPS Malta User Manual.

Table 28: Configuration options (attributes) set for instance 'maltaFpga'

AttributesValue
stoponsoftreset1



Peripheral [arm.ovpworld.org/peripheral/CoreModule9x6/1.0] instance: armSub1cm

Description
ARM Integrator Board 9x6 Core Module Registers

Limitations
none

Reference
ARM Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S, and CM1136JF-S User Guide (DUI 0138)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/IntICP/1.0] instance: armSub1pic1

Description
ARM Integrator Board interrupt controller

Limitations
none

Reference
Integrator User Guide Compact Platform Baseboard HBI-0086 (DUI 0159B)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/IntICP/1.0] instance: armSub1pic2

Description
ARM Integrator Board interrupt controller

Limitations
none

Reference
Integrator User Guide Compact Platform Baseboard HBI-0086 (DUI 0159B)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/IcpCounterTimer/1.0] instance: armSub1pit

Description
ARM Integrator Board Counter/Timer Module

Limitations
none

Reference
Integrator User Guide Compact Platform Baseboard HBI-0086 (DUI 0159B)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/IcpControl/1.0] instance: armSub1icp

Description
ARM Integrator Board Controller Module

Limitations
none

Reference
Integrator User Guide Compact Platform Baseboard HBI-0086 (DUI 0159B)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/DebugLedAndDipSwitch/1.0] instance: armSub1ld1

Description
ARM Integrator Board Debug LEDs and DIP Switch Interface

Limitations
none

Reference
Integrator User Guide Compact Platform Baseboard HBI-0086 (DUI 0159B)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/KbPL050/1.0] instance: armSub1kb1

Description
ARM PL050 PS2 Keyboard or mouse controller

Limitations
None

Reference
ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual (ARM DDI 0143)

Licensing
Open Source Apache 2.0

Table 29: Configuration options (attributes) set for instance 'armSub1kb1'

AttributesValue
isMouse0
grabDisable0



Peripheral [arm.ovpworld.org/peripheral/KbPL050/1.0] instance: armSub1ms1

Description
ARM PL050 PS2 Keyboard or mouse controller

Limitations
None

Reference
ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual (ARM DDI 0143)

Licensing
Open Source Apache 2.0

Table 30: Configuration options (attributes) set for instance 'armSub1ms1'

AttributesValue
isMouse1
grabDisable1



Peripheral [arm.ovpworld.org/peripheral/RtcPL031/1.0] instance: armSub1rtc

Description
ARM PL031 Real Time Clock (RTC)

Limitations
none

Reference
ARM PrimeCell Real Time Clock (PL031) Technical Reference Manual (ARM DDI 0224)

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: armSub1uart1

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 31: Configuration options (attributes) set for instance 'armSub1uart1'

AttributesValue
variantARM
outfileuart1.log
finishOnDisconnect1



Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: armSub1uart2

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 32: Configuration options (attributes) set for instance 'armSub1uart2'

AttributesValue
variantARM
finishOnDisconnect1



Peripheral [arm.ovpworld.org/peripheral/MmciPL181/1.0] instance: armSub1mmci

Description
ARM PrimeCell Multimedia Card Interface (MMCI)

Limitations
None

Licensing
Open Source Apache 2.0

Reference
ARM PrimeCell Multimedia Card Interface (Pl180) Technical Reference Manual (ARM DDI 0172)

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/LcdPL110/1.0] instance: armSub1lcd

Description
ARM PL110 LCD Controller

Limitations
The VGA display refresh is not optimised resulting in the VGA peripheral causing a limit on the maximum performance of a platform it contains to be around 300 MIPS (actual dependent upon refresh rate of LCD).
The LCD peripheral utilises memory watchpoints to optimise display refresh. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.
Interrupts are not supported

Reference
ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual (ARM DDI 0293)

Licensing
Open Source Apache 2.0

Table 33: Configuration options (attributes) set for instance 'armSub1lcd'

AttributesValue
noGraphics1



Peripheral [arm.ovpworld.org/peripheral/SmartLoaderArmLinux/1.0] instance: armSub1smartLoader

Licensing
Open Source Apache 2.0

Description
Psuedo-peripheral to perform memory initialisation for an ARM based Linux kernel boot: Loads Linux kernel image file and (optional) initial ram disk image into memory. Writes ATAG data into memory. Writes tiny boot code at physical memory base that configures the registers as expected by Linux Kernel and then jumps to boot address (image load address by default).

Limitations
Only supports little endian

Reference
See ARM Linux boot requirements in Linux source tree at documentation/arm/Booting

Table 34: Configuration options (attributes) set for instance 'armSub1smartLoader'

AttributesValue
disable1



Other Sites/Pages with similar information

Information on the HeteroArmNucleusMIPSLinux Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Installation, Getting Started with OVP, and Cross-Compiling Applications
http://www.ovpworld.org: Installation, Getting Started with OVP, and Cross-Compiling Applications

Two Videos on these models (from other sites)
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS