Information for MipsMalta

This page provides detailed information about the mips.ovpworld.org MipsMalta Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This is a platform representing a MIPS Malta development board. It provides the peripherals required to boot and run a Linux Operating System. A single MIPS32 architecture processor is instantiated in this platform. This instance could be duplicated to instantiate further processors to easily create an SMP platform. Attributes are provided for configuration of the generic ISA model for a specific processor. The processor model is configured to operate as a MIPS32 4KEc. The main SDRAM and Flash memory is modeled using RAM models. Both are initialised in places by the 'SmartLoaderLinux'. The SmartLoaderLinux allows ease of use of changing kernel command lines, loading an initial ram disk and creating the boot flash(s). The operation of the SmartloaderLinux is configured using a number of attributes. The kernel attribute of the SmartLoaderLinux and the imagefile of the processor must be consistent. NOTE: a non Mips Malta peripheral 'AlphaDisplay16x2' has been defined in this platform definition to be used for demo purposes. It should be removed if there is a memory error in the address space 0x18000100-0x18000103 If this platform is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Limitations
Verification has only been carried out using Little Endian memory ordering.

Reference
MIPS Malta User's Manual MD00048-2B-MALTA-USM-1.07.pdf MIPS Malta-R Development Platform User's Manual MD00627-2B-MALTA_R-USM-01.01.pdf CoreFPGA User's Manual MD00116-2B-COREFPGA-USM-01.00.pdf Linux for the MIPS Malta Development Platform User's Guide MD00646-2B-LINUXMALTA-USM-01.03.pdf

Description
Allows the address bits for the main bus to be modified (default 32)

Allows the interrupt pin used on the processor to be modified to select direct interrupts or GIC interrupts (default hwint0)

Location
The MipsMalta virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / module / MipsMalta / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processormipsle1mips.ovpworld.orgmips3234Kc
PeripheralCore_Board_SDRAM_promInitmips.ovpworld.orgSmartLoaderLinux
PeripheralsysControlmarvell.ovpworld.orgGT6412x
PeripheralPIIX4intel.ovpworld.org82371EB
PeripheralPIIX4-IDEintel.ovpworld.orgPciIDE
PeripheralPCI_PMintel.ovpworld.orgPciPM
PeripheralPCI_NETamd.ovpworld.org79C970
PeripheralintCtrlMasterintel.ovpworld.org8259A
PeripheralpciBrD_intCtrlMaster_ioovpworld.orgDynamicBridge
PeripheralpciBrD_intCtrlMaster_elcrovpworld.orgDynamicBridge
PeripheralintCtrlSlaveintel.ovpworld.org8259A
PeripheralpciBrD_intCtrlSlave_ioovpworld.orgDynamicBridge
PeripheralpciBrD_intCtrlSlave_elcrovpworld.orgDynamicBridge
Peripheral_SUPERIO_REG_ovpworld.orgSerInt
PeripheralpciBrD__SUPERIO_REG__bport1ovpworld.orgDynamicBridge
Peripheralvgacirrus.ovpworld.orgGD5446
PeripheralpciBrD_vga_configovpworld.orgDynamicBridge
Peripheralps2ifintel.ovpworld.orgPs2Control
PeripheralpciBrD_ps2if_configovpworld.orgDynamicBridge
Peripheralpitintel.ovpworld.org8253
PeripheralpciBrD_pit_bport1ovpworld.orgDynamicBridge
Peripheralrtcmotorola.ovpworld.orgMC146818
PeripheralpciBrD_rtc_busPortovpworld.orgDynamicBridge
PeripheraluartTTY0national.ovpworld.org16550
PeripheralpciBrD_uartTTY0_bport1ovpworld.orgDynamicBridge
PeripheraluartTTY1national.ovpworld.org16550
PeripheralpciBrD_uartTTY1_bport1ovpworld.orgDynamicBridge
Peripheralfd0intel.ovpworld.org82077AA
PeripheralpciBrD_fd0_bport1ovpworld.orgDynamicBridge
PeripheraluartCBUSmips.ovpworld.org16450C
PeripheralmaltaFpgamips.ovpworld.orgMaltaFPGA
PeripheralalphaDisplayovpworld.orgAlpha2x16Display
PeripheralpciBrD_alphaDisplay_busPortovpworld.orgDynamicBridge
MemoryCore_Board_SDRAMovpworld.orgram
MemoryCore_Board_SDRAM2ovpworld.orgram
MemoryMonitor_Flashovpworld.orgram
MemoryvgaMemRegionovpworld.orgrom
Busbus1(builtin)address width:addressbits
BusbusPCI(builtin)address width:32
BusbusPCIReMap(builtin)address width:32
BusPCIconfigBus(builtin)address width:16
BusPCIackBus(builtin)address width:0
BuscascadeBus(builtin)address width:3
BusflashBus(builtin)address width:32
BridgepciBr(builtin)
BridgepciMBr(builtin)
Bridgemap(builtin)
Bridgeremap1(builtin)
Bridgeremap2(builtin)
Bridgehigh2low(builtin)


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [mips.ovpworld.org/processor/mips32/1.0] instance: mipsle1

Processor model type: 'mips32' variant '34Kc' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_34Kc.pdf

Description
MIPS32 Configurable Processor Model

Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs

Features
MIPS32 Instruction set implemented
MMU Type: Standard TLB
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
MT ASE implemented
DSP ASE implemented

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'mipsle1' it has been instanced with the following parameters:

Table 3: Processor Instance 'mipsle1' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips100.0The nominal MIPS for the processor

Table 4: Processor Instance 'mipsle1' Parameters (Attributes)

Parameter NameValueType
variant34Kcenum
vectoredinterrupt0bool
config1MMUSizeM163uns32


Memory Map for processor 'mipsle1' bus: 'bus1'
Processor instance 'mipsle1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'mipsle1' is connected to bus 'bus1' using master port 'DATA'.

Table 5: Memory Map ( 'mipsle1' / 'bus1' [width: addressbits] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFCore_Board_SDRAMram
0x100000000x1BFFFFFFpciBrbridge
0x1E0000000x1E3FFFFFmapbridge
0x1F0000000x1F0008FFmaltaFpgaMaltaFPGA
0x1F0009000x1F00093FuartCBUS16450C
0x1F000A000x1F000FFFmaltaFpgaMaltaFPGA
0x1FC000000x1FC0000Fremap1bridge
0x1FC000100x1FC00013Core_Board_SDRAM_promInitSmartLoaderLinux
0x1FC000140x1FFFFFFFremap2bridge
0x200000000x5FFFFFFFCore_Board_SDRAM2ram
0x800000000xFFFFFFFFhigh2lowbridge

Table 6: Bridged Memory Map ( 'mipsle1' / 'pciBr' / 'busPCI' [width: 32] )

Lo AddressHi AddressInstanceComponent
remappableremappablePCI_NET79C970
remappableremappablePCI_PMPciPM
remappableremappablePIIX4-IDEPciIDE
remappableremappablepciBrD__SUPERIO_REG__bport1DynamicBridge
remappableremappablepciBrD_alphaDisplay_busPortDynamicBridge
remappableremappablepciBrD_fd0_bport1DynamicBridge
remappableremappablepciBrD_intCtrlMaster_elcrDynamicBridge
remappableremappablepciBrD_intCtrlMaster_ioDynamicBridge
remappableremappablepciBrD_intCtrlSlave_elcrDynamicBridge
remappableremappablepciBrD_intCtrlSlave_ioDynamicBridge
remappableremappablepciBrD_pit_bport1DynamicBridge
remappableremappablepciBrD_ps2if_configDynamicBridge
remappableremappablepciBrD_rtc_busPortDynamicBridge
remappableremappablepciBrD_uartTTY0_bport1DynamicBridge
remappableremappablepciBrD_uartTTY1_bport1DynamicBridge
remappableremappablepciBrD_vga_configDynamicBridge
remappableremappablesysControlGT6412x
remappableremappablevgaGD5446
0x100A00000x100BFFFFvgaMemRegionrom

Table 7: Bridged Memory Map ( 'mipsle1' / 'map' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram

Table 8: Bridged Memory Map ( 'mipsle1' / 'remap1' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram

Table 9: Bridged Memory Map ( 'mipsle1' / 'remap2' / 'flashBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x1E0000000x1E3FFFFFMonitor_Flashram

Table 10: Bridged Memory Map ( 'mipsle1' / 'high2low' / 'bus1' [width: addressbits] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFCore_Board_SDRAMram
0x100000000x1BFFFFFFpciBrbridge
0x1E0000000x1E3FFFFFmapbridge
0x1F0000000x1F0008FFmaltaFpgaMaltaFPGA
0x1F0009000x1F00093FuartCBUS16450C
0x1F000A000x1F000FFFmaltaFpgaMaltaFPGA
0x1FC000000x1FC0000Fremap1bridge
0x1FC000100x1FC00013Core_Board_SDRAM_promInitSmartLoaderLinux
0x1FC000140x1FFFFFFFremap2bridge
0x200000000x5FFFFFFFCore_Board_SDRAM2ram


Net Connections to processor: 'mipsle1'

Table 11: Processor Net Connections ( 'mipsle1' )

Net PortNetInstanceComponent
processorinterrupti8259IntintCtrlMaster8259A



Peripheral Instances


Peripheral [mips.ovpworld.org/peripheral/SmartLoaderLinux/1.0] instance: Core_Board_SDRAM_promInit

Licensing
Open Source Apache 2.0

Description
Smart peripheral creates memory initialisation for a MIPS32 based Linux kernel boot. Performs the generation of boot code at the reset vector (virtual address 0xbfc00000) of the MIPS32 processor. Loads both the linux kernel and initial ramdisk into memory and patches the boot code to jump to the kernel start. Initialises the MIPS32 registers and Linux command line.

Reference
MIPS Malta User Manual. MIPS Boot code reference.

Limitations
None

There are no configuration options set for this peripheral instance.


Peripheral [marvell.ovpworld.org/peripheral/GT6412x/1.0] instance: sysControl

Licensing
Open Source Apache 2.0

Description
GT64120 System Controller.
Diagnostic levels:
PCI_SLAVE 0x03
PCI_CONFIG_MASTER 0x04
PCI_EMPTY 0x08
INT_ACK 0x10
MAIN_BUS 0x20
INFO 0x40

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
GT64121A System Controller for RC4650/4700/5000 and RM526X/527X/7000 CPUs Datasheet Revision 1.0 MAR 14, 2000

There are no configuration options set for this peripheral instance.


Peripheral [intel.ovpworld.org/peripheral/82371EB/1.0] instance: PIIX4

Licensing
Open Source Apache 2.0

Description
PIIX4 PCI configuration controller.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 12: Configuration options (attributes) set for instance 'PIIX4'

AttributesValue
PCIslot10



Peripheral [intel.ovpworld.org/peripheral/PciIDE/1.0] instance: PIIX4-IDE

Licensing
Open Source Apache 2.0

Description
PCI:IDE interface. This forms part of the 82371 PIIX4 chip. It implements 4 IDE interfaces and 2 DMA controllers.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 13: Configuration options (attributes) set for instance 'PIIX4-IDE'

AttributesValue
PCIslot10
PCIfunction1



Peripheral [intel.ovpworld.org/peripheral/PciPM/1.0] instance: PCI_PM

Licensing
Open Source Apache 2.0

Description
PCI Power Manager.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 82371EB South Bridge Chipset Datasheet

Table 14: Configuration options (attributes) set for instance 'PCI_PM'

AttributesValue
PCIslot10
PCIfunction3



Peripheral [amd.ovpworld.org/peripheral/79C970/1.0] instance: PCI_NET

Licensing
Open Source Apache 2.0

Description
Implements part of the AMD AM79C97xx series Ethernet devices.
diagnosticlevel: bits 0:1 give levels for the network hardware. bits 2:3 give levels for the user:mode SLIRP interface.

Limitations
Sufficient behavior is implemented to Boot MIPS Linux and support TCP/IP protocol access.
This model implementation does not use the current BHM API features that support Ethernet interfaces. Please examine the source of the models with VLNV smsc.ovpworld.org/peripheral/LAN91*/1.0 for ones using the current BHM API implementation.

Reference
AMD Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Datasheet

Table 15: Configuration options (attributes) set for instance 'PCI_NET'

AttributesValue
PCIslot11
PCIfunction0
pollDelay1000



Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlMaster

Licensing
Open Source Apache 2.0

Description
Intel 8259A Programmable Interrupt Controller (PIT).

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.

Table 16: Configuration options (attributes) set for instance 'intCtrlMaster'

AttributesValue
spenmaster



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlMaster_io

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 17: Configuration options (attributes) set for instance 'pciBrD_intCtrlMaster_io'

AttributesValue
spLoAddress402653216
mpLoAddress402653216
portSize2
enableBridge1



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlMaster_elcr

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 18: Configuration options (attributes) set for instance 'pciBrD_intCtrlMaster_elcr'

AttributesValue
spLoAddress402654416
mpLoAddress402654416
portSize1
enableBridge1



Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlSlave

Licensing
Open Source Apache 2.0

Description
Intel 8259A Programmable Interrupt Controller (PIT).

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.

Table 19: Configuration options (attributes) set for instance 'intCtrlSlave'

AttributesValue
spenslave



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlSlave_io

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 20: Configuration options (attributes) set for instance 'pciBrD_intCtrlSlave_io'

AttributesValue
spLoAddress402653344
mpLoAddress402653344
portSize2
enableBridge1



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlSlave_elcr

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 21: Configuration options (attributes) set for instance 'pciBrD_intCtrlSlave_elcr'

AttributesValue
spLoAddress402654417
mpLoAddress402654417
portSize1
enableBridge1



Peripheral [ovpworld.org/peripheral/SerInt/1.0] instance: _SUPERIO_REG_

Description
The serial interrupt control registers in the FDC 37M817 SuperIO device.

Limitations
This is a register description only. The model does not contain any functionality.

Licensing
Open Source Apache 2.0

Reference
SMsC FDC 37M817 SuperIO device datasheet

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD__SUPERIO_REG__bport1

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 22: Configuration options (attributes) set for instance 'pciBrD__SUPERIO_REG__bport1'

AttributesValue
spLoAddress402653360
mpLoAddress402653360
portSize4
enableBridge1



Peripheral [cirrus.ovpworld.org/peripheral/GD5446/1.0] instance: vga

Licensing
Open Source Apache 2.0

Description
Cirrus CL GD5446 VGA controller.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. The VGA peripheral utilises memory mapping. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.

Reference
CL-GD5446 Preliminary Databook, Version 2.0, November 1996

Table 23: Configuration options (attributes) set for instance 'vga'

AttributesValue
scanDelay50000
PCIslot18
titleImperas MIPS32 Malta



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_vga_config

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 24: Configuration options (attributes) set for instance 'pciBrD_vga_config'

AttributesValue
spLoAddress402654128
mpLoAddress402654128
portSize48
enableBridge1



Peripheral [intel.ovpworld.org/peripheral/Ps2Control/1.0] instance: ps2if

Licensing
Open Source Apache 2.0

Description
PS2 Keyboard/Mouse Controller.

Limitations
This is a preliminary model with sufficient functionality to enable Linux to Boot on the MIPS:MALTA platform. Mouse functions are currently turned off.

Reference
SMsC FDC37M817 Super I/O Controller Datasheet

Table 25: Configuration options (attributes) set for instance 'ps2if'

AttributesValue
pollPeriod50000
grabDisable1



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_ps2if_config

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 26: Configuration options (attributes) set for instance 'pciBrD_ps2if_config'

AttributesValue
spLoAddress402653280
mpLoAddress402653280
portSize8
enableBridge1



Peripheral [intel.ovpworld.org/peripheral/8253/1.0] instance: pit

Description
Intel 8253 Programmable Interval Timer (PIT)

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. Not all modes are supported.

Licensing
Open Source Apache 2.0

Reference
Intel 8253 Datasheet. MIPS Malta Platform Reference Guide.

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_pit_bport1

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 27: Configuration options (attributes) set for instance 'pciBrD_pit_bport1'

AttributesValue
spLoAddress402653248
mpLoAddress402653248
portSize4
enableBridge1



Peripheral [motorola.ovpworld.org/peripheral/MC146818/1.0] instance: rtc

Licensing
Open Source Apache 2.0

Description
MC146818 Real:time clock.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
Motorola MC146818AS Datasheet

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_rtc_busPort

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 28: Configuration options (attributes) set for instance 'pciBrD_rtc_busPort'

AttributesValue
spLoAddress402653296
mpLoAddress402653296
portSize2
enableBridge1



Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY0

Licensing
Open Source Apache 2.0

Description
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

Table 29: Configuration options (attributes) set for instance 'uartTTY0'

AttributesValue
outfileuartTTY0.log
finishOnDisconnect1



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_uartTTY0_bport1

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 30: Configuration options (attributes) set for instance 'pciBrD_uartTTY0_bport1'

AttributesValue
spLoAddress402654200
mpLoAddress402654200
portSize8
enableBridge1



Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY1

Licensing
Open Source Apache 2.0

Description
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

Table 31: Configuration options (attributes) set for instance 'uartTTY1'

AttributesValue
outfileuartTTY1.log
finishOnDisconnect1



Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_uartTTY1_bport1

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 32: Configuration options (attributes) set for instance 'pciBrD_uartTTY1_bport1'

AttributesValue
spLoAddress402653944
mpLoAddress402653944
portSize8
enableBridge1



Peripheral [intel.ovpworld.org/peripheral/82077AA/1.0] instance: fd0

Licensing
Open Source Apache 2.0

Description
Dummy Floppy Disc Controller.

Limitations
Register stubs only.

Reference
http://www.buchty.net/casio/files/82077.pdf http://www.alldatasheet.com/datesheet-pdf/pdf/167793/INTEL/82077AA.html

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_fd0_bport1

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 33: Configuration options (attributes) set for instance 'pciBrD_fd0_bport1'

AttributesValue
spLoAddress402654192
mpLoAddress402654192
portSize8
enableBridge1



Peripheral [mips.ovpworld.org/peripheral/16450C/1.0] instance: uartCBUS

Licensing
Open Source Apache 2.0

Description
Model of 16550/16450 UART.
Special version with register addresses for MIPS MALTA C-BUS.
Connects to a bus by a slave port and optionally to a processor by an interrupt signal.
The serial input/output ports are modelled by socket connection which must be attached to a process outside the simulation environment.
Note that on start:up, the UART model will block the simulator, pending a connection to the socket.

Limitations
No modelling of baud:rate.
No modem support (DTR etc).
No support for parity.
No means to simulate errors.

Reference
MIPS Malta Datasheet

Table 34: Configuration options (attributes) set for instance 'uartCBUS'

AttributesValue
outfileuartCBUS.log



Peripheral [mips.ovpworld.org/peripheral/MaltaFPGA/1.0] instance: maltaFpga

Licensing
Open Source Apache 2.0

Description
MIPS MALTA FPGA. Drives Development board functions.

Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference
MIPS Malta User Manual.

Table 35: Configuration options (attributes) set for instance 'maltaFpga'

AttributesValue
stoponsoftreset1



Peripheral [ovpworld.org/peripheral/Alpha2x16Display/1.0] instance: alphaDisplay

Description
This is a simple test peripheral creating a 2x16 alphanumeric display.

Licensing
Open Source Apache 2.0

Limitations
This is not representing a real device and provides simple operations as an example.

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_alphaDisplay_busPort

Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.

Licensing
Open Source Apache 2.0

Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.

Reference
This is not based upon the operation of a real device

Table 36: Configuration options (attributes) set for instance 'pciBrD_alphaDisplay_busPort'

AttributesValue
spLoAddress402653440
mpLoAddress402653440
portSize4
enableBridge1



Other Sites/Pages with similar information

Information on the MipsMalta Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging Applications with INSIGHT running on OVP platforms
http://www.ovpworld.org: VMI Operating System support (VMI OS) API Reference Guide

Two Videos on these models (from other sites)
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
http://www.ovpworld.org: PowerPC Bare Metal Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS