Information for AlteraCycloneIII_3c120

This page provides detailed information about the altera.ovpworld.org AlteraCycloneIII_3c120 Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This platform models the Altera Cyclone III 3c120. The processor is an Altera Nios_II procesor, Nios_II_F.

Limitations
Peripherals are modeled only to the extent required to boot and run Operating Systems such as Linux.

Reference
Altera Cyclone III 3c120 Reference Guide

Location
The AlteraCycloneIII_3c120 virtual platform is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / module / AlteraCycloneIII_3c120 / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpualtera.ovpworld.orgnios_iiNios_II_F
Peripheraluart_s1altera.ovpworld.orgUart
Peripheralsysidaltera.ovpworld.orgSystemIDCore
Peripheraljtag_uartaltera.ovpworld.orgJtagUart
Peripheraltimer_1msaltera.ovpworld.orgIntervalTimer32Core
Memorypb_cpu_to_ddr2_botovpworld.orgram
Memorytlb_miss_ram_1kovpworld.orgram
Memoryflash_mem_64movpworld.orgram
Bussmbus(builtin)address width:32
Busiobus(builtin)address width:32
Busdbus(builtin)address width:32
Busibus(builtin)address width:32
Bridgepb_ibus_to_smbus(builtin)
Bridgepb_dbus_to_smbus_1(builtin)
Bridgepb_dbus_to_smbus_2(builtin)
Bridgepb_cpu_to_io(builtin)


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Command Line Control of the Platform

Built-in Arguments

Table 3: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.


Processor [altera.ovpworld.org/processor/nios_ii/1.0] instance: cpu

Processor model type: 'nios_ii' variant 'Nios_II_F' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/altera.ovpworld.org/processor/nios_ii/1.0/doc
- the OVP website: OVP_Model_Specific_Information_nios_ii_Nios_II_F.pdf

Description
Nios_II Family Processor Model.

Licensing
Open Source Apache 2.0

Limitations
No Custom instructions.
No Cache model.
No JTAG.

Verification
Models have been extensively tested by Imperas, and validated against tests from Altera.

Features
Barrel Shifter.
Configurable MPU.
Configurable MMU.
Shadow Register Sets.
Hardware Multiply.
Hardware Divide.
Hardware Extended Multiply.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips125.0The nominal MIPS for the processor

Table 5: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantNios_II_Fenum
BREAK_VECTOR0xc7fff820uns32
EXCEPTION_VECTOR0xd0000020uns32
RESET_VECTOR0xc2800000uns32
FAST_TLB_MISS_EXCEPTION_VECTOR0xc7fff400uns32
HW_DIVIDE1bool
HW_MULTIPLY1bool
HW_MULX0bool
INCLUDE_MMU1bool
MMU_TLB_SET_ASSOCIATIVITY16string
MMU_TLB_ENTRIES128string
MMU_PID_BITS8uns32
DATA_ADDR_WIDTH29uns32
INST_ADDR_WIDTH29uns32
TEST_HALT_EXIT1bool
EXCEPTION_EXTRA_INFORMATION1bool


Memory Map for processor 'cpu' bus: 'ibus'
Processor instance 'cpu' is connected to bus 'ibus' using master port 'INSTRUCTION'.

Table 6: Memory Map ( 'cpu' / 'ibus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFpb_ibus_to_smbusbridge

Table 7: Bridged Memory Map ( 'cpu' / 'pb_ibus_to_smbus' / 'smbus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFflash_mem_64mram
0x7FFF4000x7FFF7FFtlb_miss_ram_1kram
0x100000000x17FFFFFFpb_cpu_to_ddr2_botram


Memory Map for processor 'cpu' bus: 'dbus'
Processor instance 'cpu' is connected to bus 'dbus' using master port 'DATA'.

Table 8: Memory Map ( 'cpu' / 'dbus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x7FFFFFFpb_dbus_to_smbus_1bridge
0x80000000x87FFFFFpb_cpu_to_iobridge
0x88000000xFFFFFFFFpb_dbus_to_smbus_2bridge

Table 9: Bridged Memory Map ( 'cpu' / 'pb_dbus_to_smbus_1' / 'smbus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFflash_mem_64mram
0x7FFF4000x7FFF7FFtlb_miss_ram_1kram

Table 10: Bridged Memory Map ( 'cpu' / 'pb_cpu_to_io' / 'iobus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x4C800x4C9Fuart_s1Uart
0x4D400x4D47sysidSystemIDCore
0x4D500x4D57jtag_uartJtagUart
0x4000000x400017timer_1msIntervalTimer32Core

Table 11: Bridged Memory Map ( 'cpu' / 'pb_dbus_to_smbus_2' / 'smbus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x100000000x17FFFFFFpb_cpu_to_ddr2_botram


Net Connections to processor: 'cpu'

Table 12: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
d_irq10irq10uart_s1Uart
d_irq1irq1jtag_uartJtagUart
d_irq11irq11timer_1msIntervalTimer32Core



Peripheral Instances


Peripheral [altera.ovpworld.org/peripheral/Uart/1.0] instance: uart_s1

Licensing
Open Source Apache 2.0

Description
Altera Avalon UART

Limitations
No Support for pin level transitions

Reference
Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/SystemIDCore/1.0] instance: sysid

Licensing
Open Source Apache 2.0

Description
Altera Avalon System ID Core

Limitations
No Support for pin level transitions

Reference
Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

There are no configuration options set for this peripheral instance.


Peripheral [altera.ovpworld.org/peripheral/JtagUart/1.0] instance: jtag_uart

Licensing
Open Source Apache 2.0

Description
Altera Avalon JTAG UART

Limitations
No Support for pin level transitions

Reference
Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

Table 13: Configuration options (attributes) set for instance 'jtag_uart'

AttributesValue
writeIRQThreshold8
readIRQThreshold8
writeBufferDepth64
readBufferDepth64
console1
finishOnDisconnect1
outfilejtag_uart.log



Peripheral [altera.ovpworld.org/peripheral/IntervalTimer32Core/1.0] instance: timer_1ms

Licensing
Open Source Apache 2.0

Description
Altera Avalon Interval Timer32 Core

Limitations
No Support for pin level transitions

Reference
Altera Interval Timer Core

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the AlteraCycloneIII_3c120 Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms
http://www.ovpworld.org: DEPRECATED: OVPsim Simulation Guide - Creating, Modifying, compiling and simulating platforms using

Two Videos on these models (from other sites)
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
http://www.ovpworld.org: MIPS Demo Video Presentation


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