Information for ArmCortexMFreeRTOS
This page provides detailed information about the imperas.ovpworld.org ArmCortexMFreeRTOS Virtual Platform / Virtual Prototype.
Platform for FreeRTOS bring
Open Source Apache 2.0
BareMetal platform for bring up of FreeRTOS on ARM Cortex-M3 processor
The ArmCortexMFreeRTOS virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / module / ArmCortexMFreeRTOS / 1.0.
Table 1: Components in platform
Platform Simulation Attributes
Table 2: Platform Simulation Attributes
|stoponctrlc||stoponctrlc||Stop on control-C|
Processor [arm.ovpworld.org/processor/armm/1.0] instance: cpu1
Processor model type: 'armm' variant 'Cortex-M3' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/armm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_armm_Cortex-M3.pdf
ARMM Processor Model
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
Thumb-2 instructions are supported.
MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
Bit-band region is present. Use parameter BitBandPresent to disable it if required.
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 3: Processor Instance 'cpu1' Parameters (Configurations)
|endian||little||Select processor endian (big or little)|
|simulateexceptions||simulateexceptions||Causes the processor simulate exceptions instead of halting|
|mips||12||The nominal MIPS for the processor|
Table 4: Processor Instance 'cpu1' Parameters (Attributes)
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 5: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
|Lo Address||Hi Address||Instance||Component|
Net Connections to processor: 'cpu1'
Table 6: Processor Net Connections ( 'cpu1' )
Peripheral [ovpworld.org/peripheral/ledRegister/1.0] instance: led
Simple test peripheral providing a register that may be used to toggle LED outputs.
Open Source Apache 2.0
This is not based upon a real device
Table 7: Configuration options (attributes) set for instance 'led'
Peripheral [ti.ovpworld.org/peripheral/UartInterface/1.0] instance: UART0
UART: Universal Asynchronous Receiver Transmitter This model contains an accurate Register set interface for the TI Stellaris ARM Cortex-M3 based device.
The functionality of this model is limited. Basic status flag setting allows character reception and transmission.
FreeRTOS Cortex-M3 / GCC Port LM3S102 with GCC for Luminary Micros Stellaris microcontrollers http://www.freertos.org/portcortexgcc.html
Open Source Apache 2.0
Table 8: Configuration options (attributes) set for instance 'UART0'
Information on the ArmCortexMFreeRTOS Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms
http://www.ovpworld.org: Control File User Guide
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.