Information for ARMv8-A-FMv1

This page provides detailed information about the arm.ovpworld.org ARMv8-A-FMv1 Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This platform implements the ARM v8-A Foundation Model v1 memory map described in ARM DUI 0677C. The default processor is an ARM Cortex-A57MPx4. The processor mips rate is modeled as 500MIPS by default. The timerScaleFactor and processor MIPS rate default to values to model a 100MHz timer and CNTFREQ is automatically set accordingly. This matches the clock frequency in the default Linux device tree. These should be adjusted if that is changed.

Limitations
This platform provides the peripherals required to boot and run Operating Systems such as Linux. Some of the peripherals are register-only, non-functional models. See the individual peripheral model documentation for details.

Reference
ARM DUI 0677C

Location
The ARMv8-A-FMv1 virtual platform is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / module / ARMv8-A-FMv1 / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpuarm.ovpworld.orgarmCortex-A57MPx4
Peripheraleth0smsc.ovpworld.orgLAN91C111
PeripheralsysRegsarm.ovpworld.orgVexpressSysRegs
Peripheraluart0arm.ovpworld.orgUartPL011
Peripheraluart1arm.ovpworld.orgUartPL011
Peripheraluart2arm.ovpworld.orgUartPL011
Peripheraluart3arm.ovpworld.orgUartPL011
Peripheralvbd0ovpworld.orgVirtioBlkMMIO
PeripheralsmartLoaderarm.ovpworld.orgSmartLoaderArm64Linux
MemoryRAM0ovpworld.orgram
MemoryRAM1ovpworld.orgram
MemoryRAM2ovpworld.orgram
MemoryDRAM0ovpworld.orgram
MemoryDRAM1ovpworld.orgram
BuspBus(builtin)address width:40


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A57MPx4' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A57MPx4.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.
ARMv8 architecture models additionally require a run time model license - contact Imperas for more information.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.
Debug registers are implemented but non-functional (which is sufficient to allow operating systems such as Linux to boot). Debug state is not implemented.
The optional SIMD Cryptographic Extension instructions are not supported. AES, SHA1 and SHA2 fields in ID_AA64ISAR0_EL1 and ID_ISAR5_EL1 registers must be zero.

Verification
Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Core Features
AArch64 is implemented at EL3, EL2, EL1 and EL0.
AArch32 is implemented at EL3, EL2, EL1 and EL0.

Memory System
Security extensions are implemented (also known as TrustZone). To make non-secure accesses visible externally, override ID_AA64MMFR0_EL1.PARange to specify the required physical bus size (32, 36, 40, 42, 44, 48 or 52 bits) and connect the processor to a bus one bit wider (33, 37, 41, 43, 45, 49 or 53 bits, respectively). The extra most-significant bit is the NS bit, indicating a non-secure access. If non-secure accesses are not required to be made visible externally, connect the processor to a bus of exactly the size implied by ID_AA64MMFR0_EL1.PARange.
VMSA EL1, EL2 and EL3 stage 1 address translation is implemented. VMSA stage 2 address translation is implemented.
LPA (large physical address extension) is implemented as standard in ARMv8.

Advanced SIMD and Floating-Point Features
SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Timer
Generic Timer is present. Use parameter override_timerScaleFactor to specify the counter rate as a fraction of the processor MIPS rate (e.g. 10 implies Generic Timer counters increment once every 10 processor instructions).

Generic Interrupt Controller
GIC block is implemented (GICv2, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register GICD_CTLR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register GICD_CTLR can be observed by monitoring address 0x80001000
The internal GIC block can be disabled by raising signal GICCDISABLE, in which case the GIC needs to be modeled using a platform component instead. Input signals vfiq_CPU and virq_CPU can be used by this component to raise virtual FIQ and IRQ interrupts on cores in the cluster if required.

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter enableSystemMonitorBus is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter enableSystemBus is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips500The nominal MIPS for the processor

Table 4: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantCortex-A57MPx4enum
compatibilityISAenum
UAL1boolean
override_CBAR0x2c000000Uns32
override_GICD_TYPER_ITLines4Uns32
override_timerScaleFactor5Uns32


Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 5: Memory Map ( 'cpu' / 'pBus' [width: 40] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFRAM0ram
0x40000000x403FFFFRAM1ram
0x60000000x7FFFFFFRAM2ram
0x1A0000000x1A000FFFeth0LAN91C111
0x1C0100000x1C010FFFsysRegsVexpressSysRegs
0x1C0900000x1C090FFFuart0UartPL011
0x1C0A00000x1C0A0FFFuart1UartPL011
0x1C0B00000x1C0B0FFFuart2UartPL011
0x1C0C00000x1C0C0FFFuart3UartPL011
0x1C1300000x1C1301FFvbd0VirtioBlkMMIO
0x800000000xFFFFFFFFDRAM0ram
0x8800000000x9FFFFFFFFDRAM1ram


Net Connections to processor: 'cpu'

Table 6: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
SPI37ir5uart0UartPL011
SPI38ir6uart1UartPL011
SPI39ir7uart2UartPL011
SPI40ir8uart3UartPL011
SPI47ir15eth0LAN91C111
SPI74ir42vbd0VirtioBlkMMIO



Peripheral Instances


Peripheral [smsc.ovpworld.org/peripheral/LAN91C111/1.0] instance: eth0

Description
SMSC LAN91C111

Licensing
Open Source Apache 2.0

Limitations
Not all registers and device features are implemented. Only 16-bit bus interface currently supported.

Reference
SMSC LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (06-01-09)

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/VexpressSysRegs/1.0] instance: sysRegs

Description
ARM Versatile Express System Registers

Limitations
Only select registers are modeled. See user.c for details.

Reference
ARM Motherboard Express ATX V2M-P1 Technical Reference Manual(ARM DUI 0447G), Section 4.3 Register Summary

Licensing
Open Source Apache 2.0

Table 7: Configuration options (attributes) set for instance 'sysRegs'

AttributesValue
SYS_PROCID00x14000237



Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart0

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 8: Configuration options (attributes) set for instance 'uart0'

AttributesValue
variantARM
outfileuart0.log
finishOnDisconnect1



Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart1

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 9: Configuration options (attributes) set for instance 'uart1'

AttributesValue
variantARM
outfileuart1.log
finishOnDisconnect1



Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart2

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 10: Configuration options (attributes) set for instance 'uart2'

AttributesValue
variantARM



Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart3

Description
ARM PL011 UART

Limitations
This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing
Open Source Apache 2.0

Table 11: Configuration options (attributes) set for instance 'uart3'

AttributesValue
variantARM



Peripheral [ovpworld.org/peripheral/VirtioBlkMMIO/1.0] instance: vbd0

Description
VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO block device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf. Use the VB_DRIVE parameter to specify the disk image file to use. Set the VB_DRIVE_DELTA parameter to 1 to prevent writes to disk during simulation from changing the image file.

Limitations
Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing
Open Source Apache 2.0

Reference
http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/SmartLoaderArm64Linux/1.0] instance: smartLoader

Licensing
Open Source Apache 2.0

Description
Psuedo-peripheral to perform memory initialisation for an Arm64 Linux kernel boot: Loads Linux kernel image file, device tree blob and (optional) initial ram disk image into memory. Writes tiny boot code at physical memory base to configure regs and then jump to the Kernel entry. Modifies the device tree to always use the spin-table enable-method.

Limitations
Only supports little endian

Reference
See ARM Linux boot requirements in Linux source tree at documentation/arm64/booting.txt

Table 12: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
physicalbase0x80000000
commandconsole=ttyAMA0 earlyprintk=pl011,0x1c090000 nokaslr



Other Sites/Pages with similar information

Information on the ARMv8-A-FMv1 Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms
http://www.ovpworld.org: Using OVP Fast Processor Models with OVPsim and other simulators

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARM Bare Metal Demos Video Presentation
http://www.ovpworld.org: MIPS Demo Video Presentation


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MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
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