Information for BareMetalArm7Single
This page provides detailed information about the arm.ovpworld.org BareMetalArm7Single Virtual Platform / Virtual Prototype.
Bare Metal Platform for an ARM7 Processor. The bare metal platform instantiates a single ARM7 processor instance. The processor operates using little endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The ICM platform can be passed any application compiled to an ARM elf format. ./platform.exe application.elf
Open Source Apache 2.0
BareMetal platform for execution of ARM binary files compiled with Linaro 32-bit CrossCompiler toolchain.
None, BareMetal platform definition
The BareMetalArm7Single virtual platform is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / platform / BareMetalArm7Single / 1.0.
Table 1: Components in platform
Command Line Control of the Platform
Table 2: Platform Built-in Arguments
|allargs||allargs||The Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products|
For example: myplatform.exe -help
Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf
Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.
Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu1
Processor model type: 'arm' variant 'ARM7TDMI' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_ARM7TDMI.pdf
ARM Processor Model
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Models have been extensively tested by Imperas. ARM7TDMI models have been successfully used by customers to simulate ucLinux on Atmel virtual platforms.
Thumb instructions are supported.
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.
System Register Access Monitor
If parameter enableSystemMonitorBus is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.
System Register Implementation
If parameter enableSystemBus is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 3: Processor Instance 'cpu1' Parameters (Configurations)
|endian||little||Select processor endian (big or little)|
|mips||100||The nominal MIPS for the processor|
|semihostvendor||arm.ovpworld.org||The VLNV vendor name of a Semihost library|
|semihostname||armNewlib||The VLNV name of a Semihost library|
Table 4: Processor Instance 'cpu1' Parameters (Attributes)
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 5: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
|Lo Address||Hi Address||Instance||Component|
Net Connections to processor: 'cpu1'
There are no nets connected to this processor.
Information on the BareMetalArm7Single Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: VMI Morph Time (VMI MT) API Reference Guide
http://www.ovpworld.org: Using OVP Fast Processor Models with OVPsim and other simulators
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.