Information for BareMetalMips32Single

This page provides detailed information about the mips.ovpworld.org BareMetalMips32Single Virtual Platform / Virtual Prototype.

Description
Bare Metal Platform for an MIPS32 Processor (variant 4Km). The bare metal platform instantiates a single MIPS32 processor instance. The processor operate using big endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The ICM platform can be passed any application compiled to an MIPS32 elf format. ./platform.exe application.elf If this platform is not part of your installation, then it is available for download from www.OVPworld.org.

Licensing
Open Source Apache 2.0

Limitations
BareMetal platform for execution of MIPS MIPS32 binary files compiled with MIPS SDE CrossCompiler toolchain.

Location
The BareMetalMips32Single virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / platform / BareMetalMips32Single / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpu0mips.ovpworld.orgmips324Km
Memorymemoryovpworld.orgram
Busbus1(builtin)address width:32



Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.


Processor [mips.ovpworld.org/processor/mips32/1.0] instance: cpu0

Processor model type: 'mips32' variant '4Km' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_4Km.pdf

Description
MIPS32 Configurable Processor Model

Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.

Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs

Features
MIPS32 Instruction set implemented
MMU Type: Fixed Mapping
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu0' Parameters (Configurations)

ParameterValueDescription
endianbigSelect processor endian (big or little)
mips100The nominal MIPS for the processor
semihostvendormips.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamemips32SDEThe VLNV name of a Semihost library

Table 4: Processor Instance 'cpu0' Parameters (Attributes)

Parameter NameValueType
variant4Kmenum


Memory Map for processor 'cpu0' bus: 'bus1'
Processor instance 'cpu0' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu0' is connected to bus 'bus1' using master port 'DATA'.

Table 5: Memory Map ( 'cpu0' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemoryram


Net Connections to processor: 'cpu0'
There are no nets connected to this processor.


Other Sites/Pages with similar information

Information on the BareMetalMips32Single Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Advanced Simulation Control of Platforms and Modules User Guide
http://www.ovpworld.org: Creating Behavioral (Peripheral) components using BHM/PPM APIs and adding them to Platforms

Two Videos on these models (from other sites)
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS