Information for FreescaleVybridVFxx

This page provides detailed information about the freescale.ovpworld.org FreescaleVybridVFxx Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
Freescale Vybrid VFxx platform

Limitations
Only enough functionality modeled to boot MQX. Most peripherals modeled as dummy register ports.

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Location
The FreescaleVybridVFxx virtual platform is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / platform / FreescaleVybridVFxx / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpuarm.ovpworld.orgarmCortex-A5MPx1
Peripheralmcsmovpworld.orgdummyPort
Peripheraldma0freescale.ovpworld.orgVybridDMA
Peripheraldmamux0freescale.ovpworld.orgKinetisDMAMUX
Peripheraldmamux1freescale.ovpworld.orgKinetisDMAMUX
Peripheraluart0freescale.ovpworld.orgVybridUART
Peripheraluart1freescale.ovpworld.orgVybridUART
Peripheraluart2freescale.ovpworld.orgVybridUART
Peripheraluart3freescale.ovpworld.orgVybridUART
Peripheralspi0freescale.ovpworld.orgVybridSPI
Peripheralspi1freescale.ovpworld.orgVybridSPI
Peripheralusbc0freescale.ovpworld.orgVybridUSB
Peripheralftm0freescale.ovpworld.orgKinetisFTM
Peripheralftm1freescale.ovpworld.orgKinetisFTM
Peripheraladc0freescale.ovpworld.orgVybridADC
Peripheralquadspi0freescale.ovpworld.orgVybridQUADSPI
Peripheraliomuxcovpworld.orgdummyPort
Peripheralanadigfreescale.ovpworld.orgVybridANADIG
Peripherali2c0freescale.ovpworld.orgVybridI2C
Peripherali2c1freescale.ovpworld.orgVybridI2C
Peripheralccmfreescale.ovpworld.orgVybridCCM
Peripheraldma1freescale.ovpworld.orgVybridDMA
Peripheraldmamux2freescale.ovpworld.orgKinetisDMAMUX
Peripheraldmamux3freescale.ovpworld.orgKinetisDMAMUX
Peripheraluart4freescale.ovpworld.orgVybridUART
Peripheraluart5freescale.ovpworld.orgVybridUART
Peripheralspi3freescale.ovpworld.orgVybridSPI
Peripheralspi4freescale.ovpworld.orgVybridSPI
Peripheralddrmcovpworld.orgdummyPort
Peripheralsdhc0freescale.ovpworld.orgVybridSDHC
Peripheralsdhc1freescale.ovpworld.orgVybridSDHC
Peripheralusbc1freescale.ovpworld.orgVybridUSB
Peripheralftm2freescale.ovpworld.orgKinetisFTM
Peripheralftm3freescale.ovpworld.orgKinetisFTM
Peripheraladc1freescale.ovpworld.orgVybridADC
Peripherallcd0freescale.ovpworld.orgVybridLCD
Peripheralquadspi1freescale.ovpworld.orgVybridQUADSPI
Peripherali2c2freescale.ovpworld.orgVybridI2C
Peripherali2c3freescale.ovpworld.orgVybridI2C
Peripheralgpio0freescale.ovpworld.orgVybridGPIO
Peripheralgpio1freescale.ovpworld.orgVybridGPIO
Peripheralgpio2freescale.ovpworld.orgVybridGPIO
Peripheralgpio3freescale.ovpworld.orgVybridGPIO
Peripheralgpio4freescale.ovpworld.orgVybridGPIO
Memorybootromovpworld.orgrom
Memorysysramovpworld.orgram
BuspBus(builtin)address width:32


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Command Line Control of the Platform

Built-in Arguments

Table 3: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.


External Ports for Module FreescaleVybridVFxx

Table 4: External Ports

Port TypePort NameInternal Connection
netportp_uart0_txuart0_tx
netportp_uart0_rxuart0_rx
netportp_uart1_txuart1_tx
netportp_uart1_rxuart1_rx
netportp_uart2_txuart2_tx
netportp_uart2_rxuart2_rx
netportp_uart3_txuart3_tx
netportp_uart3_rxuart3_rx
netportp_uart4_txuart4_tx
netportp_uart4_rxuart4_rx
netportp_uart5_txuart5_tx
netportp_uart5_rxuart5_rx
netportp_gpio0_outgpio0_out
netportp_gpio0_ingpio0_in
netportp_gpio0_maskgpio0_mask
netportp_gpio1_outgpio1_out
netportp_gpio1_ingpio1_in
netportp_gpio1_maskgpio1_mask
netportp_gpio2_outgpio2_out
netportp_gpio2_ingpio2_in
netportp_gpio2_maskgpio2_mask
netportp_gpio3_outgpio3_out
netportp_gpio3_ingpio3_in
netportp_gpio3_maskgpio3_mask
netportp_gpio4_outgpio4_out
netportp_gpio4_ingpio4_in
netportp_gpio4_maskgpio4_mask



Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A5MPx1' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A5MPx1.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only except for the cycle counter, which is implemented assuming one instruction per cycle.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
Models have been extensively tested by Imperas. All functional blocks of ARM Cortex-A5 models have been extensively tested by Imperas. The configuration of the ARM Cortex-A5 models have not been verified. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Core Features
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.

Memory System
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
VMSA secure and non-secure address translation is implemented.

Advanced SIMD and Floating-Point Features
SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Interrupt Controller
GIC block is implemented (GICv1, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register ICDDCR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register ICDDCR can be observed by monitoring address 0x80001000

Debug Mask
It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x004: enable debugging of MMU/MPU mappings
Value 0x020: enable debugging of reads and writes of GIC block registers.
Value 0x040: enable debugging of exception routing via the GIC model component.
Value 0x080: enable debugging of all system register accesses.
Value 0x100: enable debugging of all traps of system register accesses.
Value 0x200: enable verbose debugging of other miscellaneous behavior (for example, the reason why a particular instruction is undefined).
Value 0x400: enable debugging of Performance Monitor timers
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

AArch32 Unpredictable Behavior
Many AArch32 instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.

Equal Target Registers
Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.

Floating Point Load/Store Multiple Lists
Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.

Floating Point VLD[2-4]/VST[2-4] Range Overflow
Instructions that load or store a fixed number of floating point registers (e.g. VST2, VLD2) are CONSTRAINED UNPREDICTABLE if the upper register bound exceeds the number of implemented floating point registers. In this model, these instructions load and store using modulo 32 indexing (consistent with AArch64 instructions with similar behavior).

If-Then (IT) Block Constraints
Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.

Use of R13
In architecture variants before ARMv8, use of R13 was described as CONSTRAINED UNPREDICTABLE in many circumstances. From ARMv8, most of these situations are no longer considered unpredictable. This model allows R13 to be used like any other GPR, consistent with the ARMv8 specification.

Use of R15
Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictable" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed (but are not interworking).
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default is "undefined".

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter "enableSystemMonitorBus" is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter "enableSystemBus" is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 5: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips396The nominal MIPS for the processor

Table 6: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantCortex-A5MPx1string
UAL1bool
override_CBAR0x40002000uns32
override_GICD_TYPER_ITLines4uns32
override_timerScaleFactor3uns32


Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 7: Memory Map ( 'cpu' / 'pBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x17FFFbootromrom
0x3F0000000x3F0FFFFFsysramram
0x400010000x40001FFFmcsmdummyPort
0x400180000x40019FFFdma0VybridDMA
0x400240000x40024FFFdmamux0KinetisDMAMUX
0x400250000x40025FFFdmamux1KinetisDMAMUX
0x400270000x40027FFFuart0VybridUART
0x400280000x40028FFFuart1VybridUART
0x400290000x40029FFFuart2VybridUART
0x4002A0000x4002AFFFuart3VybridUART
0x4002C0000x4002CFFFspi0VybridSPI
0x4002D0000x4002DFFFspi1VybridSPI
0x400340000x40034FFFusbc0VybridUSB
0x400380000x40038FFFftm0KinetisFTM
0x400390000x40039FFFftm1KinetisFTM
0x4003B0000x4003BFFFadc0VybridADC
0x400440000x40044FFFquadspi0VybridQUADSPI
0x400480000x40048FFFiomuxcdummyPort
0x400500000x40050FFFanadigVybridANADIG
0x400660000x40066FFFi2c0VybridI2C
0x400670000x40067FFFi2c1VybridI2C
0x4006B0000x4006BFFFccmVybridCCM
0x400980000x40099FFFdma1VybridDMA
0x400A10000x400A1FFFdmamux2KinetisDMAMUX
0x400A20000x400A2FFFdmamux3KinetisDMAMUX
0x400A90000x400A9FFFuart4VybridUART
0x400AA0000x400AAFFFuart5VybridUART
0x400AC0000x400ACFFFspi3VybridSPI
0x400AD0000x400ADFFFspi4VybridSPI
0x400AE0000x400AEFFFddrmcdummyPort
0x400B10000x400B1FFFsdhc0VybridSDHC
0x400B20000x400B2FFFsdhc1VybridSDHC
0x400B40000x400B4FFFusbc1VybridUSB
0x400B80000x400B8FFFftm2KinetisFTM
0x400B90000x400B9FFFftm3KinetisFTM
0x400BB0000x400BBFFFadc1VybridADC
0x400BE0000x400BEFFFlcd0VybridLCD
0x400C40000x400C4FFFquadspi1VybridQUADSPI
0x400E60000x400E6FFFi2c2VybridI2C
0x400E70000x400E7FFFi2c3VybridI2C
0x400FF0000x400FF03Fgpio0VybridGPIO
0x400FF0400x400FF07Fgpio1VybridGPIO
0x400FF0800x400FF0BFgpio2VybridGPIO
0x400FF0C00x400FF0FFgpio3VybridGPIO
0x400FF1000x400FF13Fgpio4VybridGPIO


Net Connections to processor: 'cpu'

Table 8: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
SPI93SPI93uart0VybridUART
SPI94SPI94uart1VybridUART
SPI95SPI95uart2VybridUART
SPI95SPI95uart4VybridUART
SPI96SPI96uart3VybridUART
SPI96SPI96uart5VybridUART



Peripheral Instances


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: mcsm

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridDMA/1.0] instance: dma0

Description
Freescale Vybrid Direct Memory Access Controller

Limitations
Only models control register read/write - control register CX and ECX bits are modeled as RAZ/WI

Licensing
Open Source Apache 2.0

Reference
Freescale Vybrid Peripheral User Guide

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisDMAMUX/1.0] instance: dmamux0

Description
Model of the DMAMUX peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisDMAMUX/1.0] instance: dmamux1

Description
Model of the DMAMUX peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

Table 9: Configuration options (attributes) set for instance 'dmamux1'

AttributesValue
startDMAChannel16



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart0

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 10: Configuration options (attributes) set for instance 'uart0'

AttributesValue
fifoSize16
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart1

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 11: Configuration options (attributes) set for instance 'uart1'

AttributesValue
fifoSize16
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart2

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 12: Configuration options (attributes) set for instance 'uart2'

AttributesValue
fifoSize8
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart3

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 13: Configuration options (attributes) set for instance 'uart3'

AttributesValue
fifoSize8
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridSPI/1.0] instance: spi0

Description
Model of the SPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridSPI/1.0] instance: spi1

Description
Model of the SPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridUSB/1.0] instance: usbc0

Description
Model of the USB peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisFTM/1.0] instance: ftm0

Description
Model of the FTM peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisFTM/1.0] instance: ftm1

Description
Model of the FTM peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridADC/1.0] instance: adc0

Description
Model of the ADC peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridQUADSPI/1.0] instance: quadspi0

Description
Model of the QUADSPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: iomuxc

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridANADIG/1.0] instance: anadig

Description
Analog components control digital interface

Limitations
Only models pll_lock register read

Licensing
Open Source Apache 2.0

Reference
Freescale Vybrid Peripheral User Guide

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridI2C/1.0] instance: i2c0

Description
Model of the I2C peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridI2C/1.0] instance: i2c1

Description
Model of the I2C peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridCCM/1.0] instance: ccm

Description
Freescale Clock Controller Module

Limitations
Only models status register read

Licensing
Open Source Apache 2.0

Reference
Freescale Vybrid Peripheral User Guide

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridDMA/1.0] instance: dma1

Description
Freescale Vybrid Direct Memory Access Controller

Limitations
Only models control register read/write - control register CX and ECX bits are modeled as RAZ/WI

Licensing
Open Source Apache 2.0

Reference
Freescale Vybrid Peripheral User Guide

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisDMAMUX/1.0] instance: dmamux2

Description
Model of the DMAMUX peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisDMAMUX/1.0] instance: dmamux3

Description
Model of the DMAMUX peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

Table 14: Configuration options (attributes) set for instance 'dmamux3'

AttributesValue
startDMAChannel16



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart4

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 15: Configuration options (attributes) set for instance 'uart4'

AttributesValue
fifoSize8
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridUART/1.0] instance: uart5

Description
Model of the UART peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

Table 16: Configuration options (attributes) set for instance 'uart5'

AttributesValue
fifoSize8
moduleClkFreq66000000



Peripheral [freescale.ovpworld.org/peripheral/VybridSPI/1.0] instance: spi3

Description
Model of the SPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridSPI/1.0] instance: spi4

Description
Model of the SPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: ddrmc

Description
Dummy peripheral that provides an area for accesses.

Limitations
Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing
Open Source Apache 2.0

Reference
This is not based upon a real device

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridSDHC/1.0] instance: sdhc0

Description
Model of the SDHC peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridSDHC/1.0] instance: sdhc1

Description
Model of the SDHC peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridUSB/1.0] instance: usbc1

Description
Model of the USB peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisFTM/1.0] instance: ftm2

Description
Model of the FTM peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/KinetisFTM/1.0] instance: ftm3

Description
Model of the FTM peripheral used on the Freescale Kinetis platform

Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference
www.freescale.com/Kinetis

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridADC/1.0] instance: adc1

Description
Model of the ADC peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridLCD/1.0] instance: lcd0

Description
Model of the LCD peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridQUADSPI/1.0] instance: quadspi1

Description
Model of the QUADSPI peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridI2C/1.0] instance: i2c2

Description
Model of the I2C peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridI2C/1.0] instance: i2c3

Description
Model of the I2C peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridGPIO/1.0] instance: gpio0

Description
Model of the GPIO peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridGPIO/1.0] instance: gpio1

Description
Model of the GPIO peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridGPIO/1.0] instance: gpio2

Description
Model of the GPIO peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridGPIO/1.0] instance: gpio3

Description
Model of the GPIO peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Peripheral [freescale.ovpworld.org/peripheral/VybridGPIO/1.0] instance: gpio4

Description
Model of the GPIO peripheral used on the Freescale Vybrid platform

Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms

Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013

Licensing
Open Source Apache 2.0

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the FreescaleVybridVFxx Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: VMI Programmers Views (VMI VIEW) API Reference Guide.
http://www.ovpworld.org: Simulation Control of Platforms and Modules User Guide

Two Videos on these models (from other sites)
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS