Information for iMX6S

This page provides detailed information about the nxp.ovpworld.org iMX6S Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This module implements the NXP i.MX 6 Solo application processor The i.MX6S integrates a single ARM Cortex-A9 MPCore application processor, memories and peripherals.

Limitations
Some of the peripherals are register-only, non-functional models. See the individual peripheral model documentation for details.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf)

From: https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6solo-processors-single-core-multimedia-3d-graphics-arm-cortex-a9-core:i.MX6S

Location
The iMX6S virtual platform is located in an Imperas/OVP installation at the VLNV: nxp.ovpworld.org / module / iMX6S / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorcpuarm.ovpworld.orgarmCortex-A9MPx1
PeripheralGPCnxp.ovpworld.orgiMX6_GPC
PeripheralPL310arm.ovpworld.orgL2CachePL310
PeripheralGPTnxp.ovpworld.orgiMX6_GPT
PeripheralUART1nxp.ovpworld.orgiMX6_UART
PeripheralUART2nxp.ovpworld.orgiMX6_UART
PeripheralCCMnxp.ovpworld.orgiMX6_CCM
PeripheralANALOGnxp.ovpworld.orgiMX6_Analog
PeripheralSRCnxp.ovpworld.orgiMX6_SRC
PeripheralMMDCnxp.ovpworld.orgiMX6_MMDC
PeripheralGPIO1nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO2nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO3nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO4nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO5nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO6nxp.ovpworld.orgiMX6_GPIO
PeripheralGPIO7nxp.ovpworld.orgiMX6_GPIO
PeripheraluSDHC1ovpworld.orgdynamicDummyPort
PeripheraluSDHC2ovpworld.orgdynamicDummyPort
PeripheraluSDHC3ovpworld.orgdynamicDummyPort
PeripheraluSDHC4ovpworld.orgdynamicDummyPort
PeripheralWDOG1nxp.ovpworld.orgiMX6_WDOG
PeripheralWDOG2nxp.ovpworld.orgiMX6_WDOG
PeripheralEPDCovpworld.orgdynamicDummyPort
PeripheralPXPovpworld.orgdynamicDummyPort
PeripheralSDMAovpworld.orgdynamicDummyPort
PeripheralDCIC2ovpworld.orgdynamicDummyPort
PeripheralDCIC1ovpworld.orgdynamicDummyPort
PeripheralIOMUXCovpworld.orgdynamicDummyPort
PeripheralPGC_ARMovpworld.orgdynamicDummyPort
PeripheralPGC_PUovpworld.orgdynamicDummyPort
PeripheralEPIT2ovpworld.orgdynamicDummyPort
PeripheralEPIT1ovpworld.orgdynamicDummyPort
PeripheralSNVS_HPovpworld.orgdynamicDummyPort
PeripheralUSBPHY2ovpworld.orgdynamicDummyPort
PeripheralUSBPHY1ovpworld.orgdynamicDummyPort
PeripheralKPPovpworld.orgdynamicDummyPort
PeripheralCAN2ovpworld.orgdynamicDummyPort
PeripheralCAN1ovpworld.orgdynamicDummyPort
PeripheralPWM4ovpworld.orgdynamicDummyPort
PeripheralPWM3ovpworld.orgdynamicDummyPort
PeripheralPWM2ovpworld.orgdynamicDummyPort
PeripheralPWM1ovpworld.orgdynamicDummyPort
PeripheralAIPS1_Cfgovpworld.orgdynamicDummyPort
PeripheralSPBAovpworld.orgdynamicDummyPort
PeripheralASRCovpworld.orgdynamicDummyPort
PeripheralSSI3ovpworld.orgdynamicDummyPort
PeripheralSSI2ovpworld.orgdynamicDummyPort
PeripheralSSI1ovpworld.orgdynamicDummyPort
PeripheralESAIovpworld.orgdynamicDummyPort
PeripheraleCSPI4ovpworld.orgdynamicDummyPort
PeripheraleCSPI3ovpworld.orgdynamicDummyPort
PeripheraleCSPI2ovpworld.orgdynamicDummyPort
PeripheraleCSPI1ovpworld.orgdynamicDummyPort
PeripheralSPDIFovpworld.orgdynamicDummyPort
PeripheralI2C4ovpworld.orgdynamicDummyPort
PeripheralUART5ovpworld.orgdynamicDummyPort
PeripheralUART4ovpworld.orgdynamicDummyPort
PeripheralUART3ovpworld.orgdynamicDummyPort
PeripheralVDOAovpworld.orgdynamicDummyPort
PeripheralMIPI_DSIovpworld.orgdynamicDummyPort
PeripheralMIPI_CSIovpworld.orgdynamicDummyPort
PeripheralAUDMUXovpworld.orgdynamicDummyPort
PeripheralTZASC2ovpworld.orgdynamicDummyPort
PeripheralTZASC1ovpworld.orgdynamicDummyPort
PeripheralCSUovpworld.orgdynamicDummyPort
PeripheralOCOTP_CTRLovpworld.orgdynamicDummyPort
PeripheralEIMovpworld.orgdynamicDummyPort
PeripheralMMDCp1ovpworld.orgdynamicDummyPort
PeripheralROMCPovpworld.orgdynamicDummyPort
PeripheralI2C3ovpworld.orgdynamicDummyPort
PeripheralI2C2ovpworld.orgdynamicDummyPort
PeripheralI2C1ovpworld.orgdynamicDummyPort
PeripheralMLB150ovpworld.orgdynamicDummyPort
PeripheralENETovpworld.orgdynamicDummyPort
PeripheralUSBOH3_USBovpworld.orgdynamicDummyPort
PeripheralUSBOH3_PL301ovpworld.orgdynamicDummyPort
PeripheralAIPS2_Cfgovpworld.orgdynamicDummyPort
PeripheralCAAMovpworld.orgdynamicDummyPort
PeripheralIPUovpworld.orgdynamicDummyPort
PeripheralGPU2Dovpworld.orgdynamicDummyPort
PeripheralGPU3Dovpworld.orgdynamicDummyPort
PeripheralHDMIovpworld.orgdynamicDummyPort
PeripheralAPBH_DMAovpworld.orgdynamicDummyPort
PeripheralsmartLoaderarm.ovpworld.orgSmartLoaderArmLinux
PeripheralVBD0ovpworld.orgVirtioBlkMMIO
MemoryOCRAMovpworld.orgram
MemoryEIM-RAMovpworld.orgram
MemoryDRAMovpworld.orgram
BuspBus(builtin)address width:32


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A9MPx1' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A9MPx1.pdf

Description
ARM Processor Model

Licensing
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only except for the cycle counter, which is implemented assuming one instruction per cycle.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Core Features
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.

Memory System
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
VMSA secure and non-secure address translation is implemented.

Advanced SIMD and Floating-Point Features
SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Interrupt Controller
GIC block is implemented (GICv1, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register ICDDCR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register ICDDCR can be observed by monitoring address 0x80001000

Debug Mask
It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x004: enable debugging of MMU/MPU mappings
Value 0x020: enable debugging of reads and writes of GIC block registers.
Value 0x040: enable debugging of exception routing via the GIC model component.
Value 0x080: enable debugging of all system register accesses.
Value 0x100: enable debugging of all traps of system register accesses.
Value 0x200: enable verbose debugging of other miscellaneous behavior (for example, the reason why a particular instruction is undefined).
Value 0x400: enable debugging of Performance Monitor timers
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

AArch32 Unpredictable Behavior
Many AArch32 instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.

Equal Target Registers
Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.

Floating Point Load/Store Multiple Lists
Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.

Floating Point VLD[2-4]/VST[2-4] Range Overflow
Instructions that load or store a fixed number of floating point registers (e.g. VST2, VLD2) are CONSTRAINED UNPREDICTABLE if the upper register bound exceeds the number of implemented floating point registers. In this model, these instructions load and store using modulo 32 indexing (consistent with AArch64 instructions with similar behavior).

If-Then (IT) Block Constraints
Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.

Use of R13
In architecture variants before ARMv8, use of R13 was described as CONSTRAINED UNPREDICTABLE in many circumstances. From ARMv8, most of these situations are no longer considered unpredictable. This model allows R13 to be used like any other GPR, consistent with the ARMv8 specification.

Use of R15
Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictable" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed (but are not interworking).
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default is "undefined".

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query
Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query
A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address. Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively, and register PTWAddressValid is a bitmask indicating which address registers contain valid data: for example, the value 0xe indicates that PTWAddressL1-PTWAddressL3 are valid but PTWAddressL0 is not. Registers PTWValueL0-PTWValueL3 contain entry values read at level 0 to level 3. Register PTWInput contains the input address that starts a walk and Register PTWOutput contains the result address (valid only if the page table walk completes). Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput and bit 6 indicates PTWOutput.

Artifact Page Table Walks
Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events
Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations
A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

Halt Reason Introspection
An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor
If parameter "enableSystemMonitorBus" is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation
If parameter "enableSystemBus" is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips800The nominal MIPS for the processor

Table 4: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
variantCortex-A9MPx1enum
compatibilityISAenum
UAL1boolean
override_CBAR0x00a00000Uns32
override_MIDR0x411fc090Uns32
override_GICD_TYPER_ITLines4uns32


Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 5: Memory Map ( 'cpu' / 'pBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
remappableremappableAIPS1_CfgdynamicDummyPort
remappableremappableAIPS2_CfgdynamicDummyPort
remappableremappableAPBH_DMAdynamicDummyPort
remappableremappableASRCdynamicDummyPort
remappableremappableAUDMUXdynamicDummyPort
remappableremappableCAAMdynamicDummyPort
remappableremappableCAN1dynamicDummyPort
remappableremappableCAN2dynamicDummyPort
remappableremappableCSUdynamicDummyPort
remappableremappableDCIC1dynamicDummyPort
remappableremappableDCIC2dynamicDummyPort
remappableremappableEIMdynamicDummyPort
remappableremappableENETdynamicDummyPort
remappableremappableEPDCdynamicDummyPort
remappableremappableEPIT1dynamicDummyPort
remappableremappableEPIT2dynamicDummyPort
remappableremappableESAIdynamicDummyPort
remappableremappableGPU2DdynamicDummyPort
remappableremappableGPU3DdynamicDummyPort
remappableremappableHDMIdynamicDummyPort
remappableremappableI2C1dynamicDummyPort
remappableremappableI2C2dynamicDummyPort
remappableremappableI2C3dynamicDummyPort
remappableremappableI2C4dynamicDummyPort
remappableremappableIOMUXCdynamicDummyPort
remappableremappableIPUdynamicDummyPort
remappableremappableKPPdynamicDummyPort
remappableremappableMIPI_CSIdynamicDummyPort
remappableremappableMIPI_DSIdynamicDummyPort
remappableremappableMLB150dynamicDummyPort
remappableremappableMMDCp1dynamicDummyPort
remappableremappableOCOTP_CTRLdynamicDummyPort
remappableremappablePGC_ARMdynamicDummyPort
remappableremappablePGC_PUdynamicDummyPort
remappableremappablePWM1dynamicDummyPort
remappableremappablePWM2dynamicDummyPort
remappableremappablePWM3dynamicDummyPort
remappableremappablePWM4dynamicDummyPort
remappableremappablePXPdynamicDummyPort
remappableremappableROMCPdynamicDummyPort
remappableremappableSDMAdynamicDummyPort
remappableremappableSNVS_HPdynamicDummyPort
remappableremappableSPBAdynamicDummyPort
remappableremappableSPDIFdynamicDummyPort
remappableremappableSSI1dynamicDummyPort
remappableremappableSSI2dynamicDummyPort
remappableremappableSSI3dynamicDummyPort
remappableremappableTZASC1dynamicDummyPort
remappableremappableTZASC2dynamicDummyPort
remappableremappableUART3dynamicDummyPort
remappableremappableUART4dynamicDummyPort
remappableremappableUART5dynamicDummyPort
remappableremappableUSBOH3_PL301dynamicDummyPort
remappableremappableUSBOH3_USBdynamicDummyPort
remappableremappableUSBPHY1dynamicDummyPort
remappableremappableUSBPHY2dynamicDummyPort
remappableremappableVDOAdynamicDummyPort
remappableremappableeCSPI1dynamicDummyPort
remappableremappableeCSPI2dynamicDummyPort
remappableremappableeCSPI3dynamicDummyPort
remappableremappableeCSPI4dynamicDummyPort
remappableremappableuSDHC1dynamicDummyPort
remappableremappableuSDHC2dynamicDummyPort
remappableremappableuSDHC3dynamicDummyPort
remappableremappableuSDHC4dynamicDummyPort
0x9000000x91FFFFOCRAMram
0xA020000xA02FFFPL310L2CachePL310
0x20200000x2023FFFUART1iMX6_UART
0x20980000x2098FFFGPTiMX6_GPT
0x209C0000x209FFFFGPIO1iMX6_GPIO
0x20A00000x20A3FFFGPIO2iMX6_GPIO
0x20A40000x20A7FFFGPIO3iMX6_GPIO
0x20A80000x20ABFFFGPIO4iMX6_GPIO
0x20AC0000x20AFFFFGPIO5iMX6_GPIO
0x20B00000x20B3FFFGPIO6iMX6_GPIO
0x20B40000x20B7FFFGPIO7iMX6_GPIO
0x20BC0000x20BFFFFWDOG1iMX6_WDOG
0x20C00000x20C3FFFWDOG2iMX6_WDOG
0x20C40000x20C4FFFCCMiMX6_CCM
0x20C80000x20C8FFFANALOGiMX6_Analog
0x20D80000x20DBFFFSRCiMX6_SRC
0x20DC0000x20DC25FGPCiMX6_GPC
0x21B00000x21B3FFFMMDCiMX6_MMDC
0x21E80000x21EBFFFUART2iMX6_UART
0x21FF0000x21FF1FFVBD0VirtioBlkMMIO
0x80000000xFFFFFFFEIM-RAMram
0x100000000x2FFFFFFFDRAMram


Net Connections to processor: 'cpu'

Table 6: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
SPI32IOMUXC_spiGPCiMX6_GPC
SPI33DAP_spiGPCiMX6_GPC
SPI34SDMA_spiGPCiMX6_GPC
SPI35VPU_spiGPCiMX6_GPC
SPI36SNVS_spiGPCiMX6_GPC
SPI37IPU_spiGPCiMX6_GPC
SPI38IPU1_spiGPCiMX6_GPC
SPI41GPU3D_spiGPCiMX6_GPC
SPI42R2D_spiGPCiMX6_GPC
SPI44VPU_jpeg_spiGPCiMX6_GPC
SPI45APBH_spiGPCiMX6_GPC
SPI46EIM_spiGPCiMX6_GPC
SPI47BCH_spiGPCiMX6_GPC
SPI48GPMI_spiGPCiMX6_GPC
SPI49DTCP_spiGPCiMX6_GPC
SPI50VDOA_spiGPCiMX6_GPC
SPI51SNVS_consolidated_spiGPCiMX6_GPC
SPI52SNVS_security_spiGPCiMX6_GPC
SPI53CSU_spiGPCiMX6_GPC
SPI58UART1_spiGPCiMX6_GPC
SPI58UART1_spiUART1iMX6_UART
SPI59UART2_spiGPCiMX6_GPC
SPI59UART2_spiUART2iMX6_UART
SPI60UART3_spiGPCiMX6_GPC
SPI61UART4_spiGPCiMX6_GPC
SPI62UART5_spiGPCiMX6_GPC
SPI63eCSPI1_spiGPCiMX6_GPC
SPI64eCSPI2_spiGPCiMX6_GPC
SPI65eCSPI3_spiGPCiMX6_GPC
SPI66eCSPI4_spiGPCiMX6_GPC
SPI67I2C4_spiGPCiMX6_GPC
SPI68I2C1_spiGPCiMX6_GPC
SPI69I2C2_spiGPCiMX6_GPC
SPI70I2C3_spiGPCiMX6_GPC
SPI72USBHost1_spiGPCiMX6_GPC
SPI73USBHost2_spiGPCiMX6_GPC
SPI74USBHost3_spiGPCiMX6_GPC
SPI75USBOTG_spiGPCiMX6_GPC
SPI76USB_PHYUTMI0_spiGPCiMX6_GPC
SPI77USB_PHYUTMI1_spiGPCiMX6_GPC
SPI78SSI1_spiGPCiMX6_GPC
SPI79SSI2_spiGPCiMX6_GPC
SPI80SSI3_spiGPCiMX6_GPC
SPI81TMTS_spiGPCiMX6_GPC
SPI82ASRC_spiGPCiMX6_GPC
SPI83ESAI_spiGPCiMX6_GPC
SPI84SPDIF_spiGPCiMX6_GPC
SPI85MLB150_err_spiGPCiMX6_GPC
SPI86PMU_analog_spiGPCiMX6_GPC
SPI87GPT_spiGPCiMX6_GPC
SPI87GPT_spiGPTiMX6_GPT
SPI88EPIT1_spiGPCiMX6_GPC
SPI89EPIT2_spiGPCiMX6_GPC
SPI90GPIO1_int7_spiGPCiMX6_GPC
SPI91GPIO1_int6_spiGPCiMX6_GPC
SPI92GPIO1_int5_spiGPCiMX6_GPC
SPI93GPIO1_int4_spiGPCiMX6_GPC
SPI94GPIO1_int3_spiGPCiMX6_GPC
SPI95GPIO1_int2_spiGPCiMX6_GPC
SPI96GPIO1_int1_spiGPCiMX6_GPC
SPI97GPIO1_int0_spiGPCiMX6_GPC
SPI98GPIO1_s0_15_spiGPCiMX6_GPC
SPI99GPIO1_s16_31_spiGPCiMX6_GPC
SPI100GPIO2_s0_15_spiGPCiMX6_GPC
SPI101GPIO2_s16_31_spiGPCiMX6_GPC
SPI102GPIO3_s0_15_spiGPCiMX6_GPC
SPI103GPIO3_s16_31_spiGPCiMX6_GPC
SPI104GPIO4_s0_15_spiGPCiMX6_GPC
SPI105GPIO4_s16_31_spiGPCiMX6_GPC
SPI106GPIO5_s0_15_spiGPCiMX6_GPC
SPI107GPIO5_s16_31_spiGPCiMX6_GPC
SPI108GPIO6_s0_15_spiGPCiMX6_GPC
SPI109GPIO6_s16_31_spiGPCiMX6_GPC
SPI110GPIO7_s0_15_spiGPCiMX6_GPC
SPI111GPIO7_s16_31_spiGPCiMX6_GPC
SPI112WDOG1_spiGPCiMX6_GPC
SPI112WDOG1_spiWDOG1iMX6_WDOG
SPI113WDOG2_spiGPCiMX6_GPC
SPI113WDOG2_spiWDOG2iMX6_WDOG
SPI114KPP_spiGPCiMX6_GPC
SPI115PWM1_spiGPCiMX6_GPC
SPI116PWM2_spiGPCiMX6_GPC
SPI117PWM3_spiGPCiMX6_GPC
SPI118PWM4_spiGPCiMX6_GPC
SPI119CCM1_spiGPCiMX6_GPC
SPI120CCM2_spiGPCiMX6_GPC
SPI121GPC1_spiGPCiMX6_GPC
SPI123SRC_spiGPCiMX6_GPC
SPI124CPU_L2_spiGPCiMX6_GPC
SPI125CPU_ParityCheckError_spiGPCiMX6_GPC
SPI126CPU_Performance_Unit_spiGPCiMX6_GPC
SPI127CPU_CTI_spiGPCiMX6_GPC
SPI128SRC_wdog_spiGPCiMX6_GPC
SPI129EPDC_spiGPCiMX6_GPC
SPI130PXP_spiGPCiMX6_GPC
SPI132MIPI_CSI1_spiGPCiMX6_GPC
SPI133MIPI_CSI2_spiGPCiMX6_GPC
SPI134MIPI_DSI_spiGPCiMX6_GPC
SPI135MIPI_HSI_spiGPCiMX6_GPC
SPI136SJC_spiGPCiMX6_GPC
SPI137CAAM0_spiGPCiMX6_GPC
SPI138CAAM1_spiGPCiMX6_GPC
SPI140TZASC1_spiGPCiMX6_GPC
SPI141TZASC2_spiGPCiMX6_GPC
SPI142FLEXCAN1_spiGPCiMX6_GPC
SPI143FLEXCAN2_spiGPCiMX6_GPC
SPI147HDMI_spiGPCiMX6_GPC
SPI148HDMICEC_spiGPCiMX6_GPC
SPI149MLB150_irq0_31_spiGPCiMX6_GPC
SPI150ENET_spiGPCiMX6_GPC
SPI151ENET_timer_spiGPCiMX6_GPC
SPI152PCIe1_spiGPCiMX6_GPC
SPI153PCIe2_spiGPCiMX6_GPC
SPI154PCIe3_spiGPCiMX6_GPC
SPI155PCIe4_spiGPCiMX6_GPC
SPI156DCIC1_spiGPCiMX6_GPC
SPI157DCIC2_spiGPCiMX6_GPC
SPI158MLB150_irq32_63_spiGPCiMX6_GPC
SPI159PMU_digital_spiGPCiMX6_GPC
reset_CPU0reset_A9_CPU0SRCiMX6_SRC
SPI39VBD0_spiVBD0VirtioBlkMMIO



Peripheral Instances


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPC/1.0] instance: GPC

Description
NXP i.MX6 GPC General Power Controller

Licensing
Open Source Apache 2.0

Limitations
This is a register only model

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [arm.ovpworld.org/peripheral/L2CachePL310/1.0] instance: PL310

Description
ARM PL310 L2 Cache Control Registers

Licensing
Open Source Apache 2.0

Limitations
Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference
ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual (ARM DDI 0246)

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPT/1.0] instance: GPT

Description
NXP i.MX6 GPT General Purpose Timer

Licensing
Open Source Apache 2.0

Limitations
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_UART/1.0] instance: UART1

Description
iMX6 UART

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the UART.
It has basic functionality to support the iMX6 platform, Rx and Tx of data only.
There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

Table 7: Configuration options (attributes) set for instance 'UART1'

AttributesValue
outfileUART1.log
finishOnDisconnect1
console1



Peripheral [nxp.ovpworld.org/peripheral/iMX6_UART/1.0] instance: UART2

Description
iMX6 UART

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the UART.
It has basic functionality to support the iMX6 platform, Rx and Tx of data only.
There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

Table 8: Configuration options (attributes) set for instance 'UART2'

AttributesValue
outfileUART2.log
finishOnDisconnect1
console0



Peripheral [nxp.ovpworld.org/peripheral/iMX6_CCM/1.0] instance: CCM

Description
NXP i.MX6 CCM Clock Controller Module

Licensing
Open Source Apache 2.0

Limitations
This is a register only interface model. No functionality is implemented. The reset value for the CCM_CSCDR2 epdc_pix_clk_sel field (bits 11:9) has been modified from the documented value. The documented value (0x5) is reserved and causes a Linux Kernel Panic

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_Analog/1.0] instance: ANALOG

Description
NXP i.MX6 ANALOG: (PLLs, PFDs, Regulators, LDOs, Temp Sensor) Registers

Licensing
Open Source Apache 2.0

Limitations
This is a register only interface model. No functionality is implemented. The reset values for registers have been modified from those specified in the documentation to set the lock bit (bit 31) on PLL registers.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_SRC/1.0] instance: SRC

Description
NXP i.MX6 System Reset Control (SRC)

Licensing
Open Source Apache 2.0

Limitations
Implements the power on reset and core1 enable requirements.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_MMDC/1.0] instance: MMDC

Description
NXP i.MX6 MMDC

Licensing
Open Source Apache 2.0

Limitations
This is a register only model with acknowledgement of auto power saving

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO1

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO2

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO3

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO4

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO5

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO6

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_GPIO/1.0] instance: GPIO7

Description
NXP i.MX6 GPIO

Licensing
Open Source Apache 2.0

Limitations
No behaviour is implemented.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: uSDHC1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 9: Configuration options (attributes) set for instance 'uSDHC1'

AttributesValue
portAddress0x02190000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: uSDHC2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 10: Configuration options (attributes) set for instance 'uSDHC2'

AttributesValue
portAddress0x02194000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: uSDHC3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 11: Configuration options (attributes) set for instance 'uSDHC3'

AttributesValue
portAddress0x02198000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: uSDHC4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 12: Configuration options (attributes) set for instance 'uSDHC4'

AttributesValue
portAddress0x0219C000
portSize16384
cbEnableTrue



Peripheral [nxp.ovpworld.org/peripheral/iMX6_WDOG/1.0] instance: WDOG1

Description
iMX6 WDOG

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the WDOG.
It has basic functionality to support the iMX6 platform.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [nxp.ovpworld.org/peripheral/iMX6_WDOG/1.0] instance: WDOG2

Description
iMX6 WDOG

Licensing
Open Source Apache 2.0

Limitations
This is an incomplete model of the WDOG.
It has basic functionality to support the iMX6 platform.

Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: EPDC

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 13: Configuration options (attributes) set for instance 'EPDC'

AttributesValue
portAddress0x020F4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PXP

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 14: Configuration options (attributes) set for instance 'PXP'

AttributesValue
portAddress0x020F0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SDMA

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 15: Configuration options (attributes) set for instance 'SDMA'

AttributesValue
portAddress0x020EC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: DCIC2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 16: Configuration options (attributes) set for instance 'DCIC2'

AttributesValue
portAddress0x020E8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: DCIC1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 17: Configuration options (attributes) set for instance 'DCIC1'

AttributesValue
portAddress0x020E4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: IOMUXC

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 18: Configuration options (attributes) set for instance 'IOMUXC'

AttributesValue
portAddress0x020E0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PGC_ARM

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 19: Configuration options (attributes) set for instance 'PGC_ARM'

AttributesValue
portAddress0x020DC2A0
portSize32
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PGC_PU

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 20: Configuration options (attributes) set for instance 'PGC_PU'

AttributesValue
portAddress0x020DC260
portSize32
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: EPIT2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 21: Configuration options (attributes) set for instance 'EPIT2'

AttributesValue
portAddress0x020D4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: EPIT1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 22: Configuration options (attributes) set for instance 'EPIT1'

AttributesValue
portAddress0x020D0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SNVS_HP

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 23: Configuration options (attributes) set for instance 'SNVS_HP'

AttributesValue
portAddress0x020CC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: USBPHY2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 24: Configuration options (attributes) set for instance 'USBPHY2'

AttributesValue
portAddress0x020CA000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: USBPHY1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 25: Configuration options (attributes) set for instance 'USBPHY1'

AttributesValue
portAddress0x020C9000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: KPP

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 26: Configuration options (attributes) set for instance 'KPP'

AttributesValue
portAddress0x020B8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: CAN2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 27: Configuration options (attributes) set for instance 'CAN2'

AttributesValue
portAddress0x02094000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: CAN1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 28: Configuration options (attributes) set for instance 'CAN1'

AttributesValue
portAddress0x02090000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PWM4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 29: Configuration options (attributes) set for instance 'PWM4'

AttributesValue
portAddress0x0208C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PWM3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 30: Configuration options (attributes) set for instance 'PWM3'

AttributesValue
portAddress0x02088000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PWM2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 31: Configuration options (attributes) set for instance 'PWM2'

AttributesValue
portAddress0x02084000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: PWM1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 32: Configuration options (attributes) set for instance 'PWM1'

AttributesValue
portAddress0x02080000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: AIPS1_Cfg

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 33: Configuration options (attributes) set for instance 'AIPS1_Cfg'

AttributesValue
portAddress0x0207C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SPBA

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 34: Configuration options (attributes) set for instance 'SPBA'

AttributesValue
portAddress0x0203C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: ASRC

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 35: Configuration options (attributes) set for instance 'ASRC'

AttributesValue
portAddress0x02034000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SSI3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 36: Configuration options (attributes) set for instance 'SSI3'

AttributesValue
portAddress0x02030000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SSI2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 37: Configuration options (attributes) set for instance 'SSI2'

AttributesValue
portAddress0x0202C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SSI1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 38: Configuration options (attributes) set for instance 'SSI1'

AttributesValue
portAddress0x02028000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: ESAI

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 39: Configuration options (attributes) set for instance 'ESAI'

AttributesValue
portAddress0x02024000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: eCSPI4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 40: Configuration options (attributes) set for instance 'eCSPI4'

AttributesValue
portAddress0x02014000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: eCSPI3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 41: Configuration options (attributes) set for instance 'eCSPI3'

AttributesValue
portAddress0x02010000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: eCSPI2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 42: Configuration options (attributes) set for instance 'eCSPI2'

AttributesValue
portAddress0x0200C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: eCSPI1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 43: Configuration options (attributes) set for instance 'eCSPI1'

AttributesValue
portAddress0x02008000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: SPDIF

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 44: Configuration options (attributes) set for instance 'SPDIF'

AttributesValue
portAddress0x02004000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: I2C4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 45: Configuration options (attributes) set for instance 'I2C4'

AttributesValue
portAddress0x021F8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: UART5

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 46: Configuration options (attributes) set for instance 'UART5'

AttributesValue
portAddress0x021F4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: UART4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 47: Configuration options (attributes) set for instance 'UART4'

AttributesValue
portAddress0x021F0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: UART3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 48: Configuration options (attributes) set for instance 'UART3'

AttributesValue
portAddress0x021EC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: VDOA

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 49: Configuration options (attributes) set for instance 'VDOA'

AttributesValue
portAddress0x021E4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: MIPI_DSI

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 50: Configuration options (attributes) set for instance 'MIPI_DSI'

AttributesValue
portAddress0x021E0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: MIPI_CSI

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 51: Configuration options (attributes) set for instance 'MIPI_CSI'

AttributesValue
portAddress0x021DC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: AUDMUX

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 52: Configuration options (attributes) set for instance 'AUDMUX'

AttributesValue
portAddress0x021D8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: TZASC2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 53: Configuration options (attributes) set for instance 'TZASC2'

AttributesValue
portAddress0x021D4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: TZASC1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 54: Configuration options (attributes) set for instance 'TZASC1'

AttributesValue
portAddress0x021D0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: CSU

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 55: Configuration options (attributes) set for instance 'CSU'

AttributesValue
portAddress0x021C0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: OCOTP_CTRL

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 56: Configuration options (attributes) set for instance 'OCOTP_CTRL'

AttributesValue
portAddress0x021BC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: EIM

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 57: Configuration options (attributes) set for instance 'EIM'

AttributesValue
portAddress0x021B8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: MMDCp1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 58: Configuration options (attributes) set for instance 'MMDCp1'

AttributesValue
portAddress0x021B4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: ROMCP

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 59: Configuration options (attributes) set for instance 'ROMCP'

AttributesValue
portAddress0x021AC000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: I2C3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 60: Configuration options (attributes) set for instance 'I2C3'

AttributesValue
portAddress0x021A8000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: I2C2

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 61: Configuration options (attributes) set for instance 'I2C2'

AttributesValue
portAddress0x021A4000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: I2C1

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 62: Configuration options (attributes) set for instance 'I2C1'

AttributesValue
portAddress0x021A0000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: MLB150

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 63: Configuration options (attributes) set for instance 'MLB150'

AttributesValue
portAddress0x0218C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: ENET

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 64: Configuration options (attributes) set for instance 'ENET'

AttributesValue
portAddress0x02188000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: USBOH3_USB

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 65: Configuration options (attributes) set for instance 'USBOH3_USB'

AttributesValue
portAddress0x02184000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: USBOH3_PL301

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 66: Configuration options (attributes) set for instance 'USBOH3_PL301'

AttributesValue
portAddress0x02180000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: AIPS2_Cfg

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 67: Configuration options (attributes) set for instance 'AIPS2_Cfg'

AttributesValue
portAddress0x0217C000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: CAAM

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 68: Configuration options (attributes) set for instance 'CAAM'

AttributesValue
portAddress0x02100000
portSize65536
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: IPU

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 69: Configuration options (attributes) set for instance 'IPU'

AttributesValue
portAddress0x02600000
portSize4194304
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: GPU2D

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 70: Configuration options (attributes) set for instance 'GPU2D'

AttributesValue
portAddress0x00134000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: GPU3D

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 71: Configuration options (attributes) set for instance 'GPU3D'

AttributesValue
portAddress0x00130000
portSize16384
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: HDMI

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 72: Configuration options (attributes) set for instance 'HDMI'

AttributesValue
portAddress0x00120000
portSize36864
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: APBH_DMA

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 73: Configuration options (attributes) set for instance 'APBH_DMA'

AttributesValue
portAddress0x00110000
portSize8192
cbEnableTrue



Peripheral [arm.ovpworld.org/peripheral/SmartLoaderArmLinux/1.0] instance: smartLoader

Licensing
Open Source Apache 2.0

Description
Psuedo-peripheral to perform memory initialisation for an ARM based Linux kernel boot: Loads Linux kernel image file and (optional) initial ram disk image into memory. Writes ATAG data into memory. Writes tiny boot code at physical memory base that configures the registers as expected by Linux Kernel and then jumps to boot address (image load address by default).

Limitations
Only supports little endian

Reference
See ARM Linux boot requirements in Linux source tree at documentation/arm/Booting

Table 74: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
physicalbase0x10000000
memsize0x20000000
kerneladdr0x11000000



Peripheral [ovpworld.org/peripheral/VirtioBlkMMIO/1.0] instance: VBD0

Description
VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO block device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf. Use the VB_DRIVE parameter to specify the disk image file to use. Set the VB_DRIVE_DELTA parameter to 1 to prevent writes to disk during simulation from changing the image file.

Limitations
Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing
Open Source Apache 2.0

Reference
http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the iMX6S Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms
http://www.ovpworld.org: Debugging Applications with GDB running on OVP platforms

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARC Demo Video Presentation
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS