Information for Or1kUclinux
This page provides detailed information about the imperas.ovpworld.org Or1kUclinux Virtual Platform / Virtual Prototype.
Platform for an Or1k Processor to execute uCLinux.
Open Source Apache 2.0
Provides sufficient functionality to execute uCLinux operating system and OR1K elf files
The Or1kUclinux virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / platform / Or1kUclinux / 1.0.
Table 1: Components in platform
Processor [ovpworld.org/processor/or1k/1.0] instance: cpu1
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 2: Processor Instance 'cpu1' Parameters (Configurations)
|mips||100||The nominal MIPS for the processor|
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 3: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
|Lo Address||Hi Address||Instance||Component|
Net Connections to processor: 'cpu1'
Table 4: Processor Net Connections ( 'cpu1' )
Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uart1
Open Source Apache 2.0
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)
There are no configuration options set for this peripheral instance.
Information on the Or1kUclinux Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: Debugging Applications with Eclipse running on OVP platforms
http://www.ovpworld.org: Creating Instruction Accurate Processor models using the VMI API
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
http://www.ovpworld.org: ARC Demo Video Presentation
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.