Information for virtio

This page provides detailed information about the riscv.ovpworld.org virtio Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
Virtio System Platform to boot BusyBear-Linux Kernel

Reference
Virtio System Platform

Limitations
Sufficient functionality to boot BusyBear-Linux Kernel using the Virtio platform

Location
The virtio virtual platform is located in an Imperas/OVP installation at the VLNV: riscv.ovpworld.org / module / virtio / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processorhart0riscv.ovpworld.orgriscvRV64GC
PeripheralVBD0ovpworld.orgVirtioBlkMMIO
PeripheralVND0ovpworld.orgVirtioNetMMIO
Peripheralvirtio_mmio3ovpworld.orgdynamicDummyPort
Peripheralvirtio_mmio4ovpworld.orgdynamicDummyPort
Peripheralvirtio_mmio5ovpworld.orgdynamicDummyPort
Peripheralvirtio_mmio6ovpworld.orgdynamicDummyPort
Peripheralvirtio_mmio7ovpworld.orgdynamicDummyPort
Peripheralvirtio_mmio8ovpworld.orgdynamicDummyPort
Peripheralclintriscv.ovpworld.orgCLINT
Peripheralplicriscv.ovpworld.orgPLIC
PeripheraluartTTY0national.ovpworld.org16550
PeripheralsmartLoaderriscv.ovpworld.orgSmartLoaderRV64Linux
Memorybootramovpworld.orgram
Memorymainovpworld.orgram
Busbus0(builtin)address width:48


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [riscv.ovpworld.org/processor/riscv/1.0] instance: hart0

Processor model type: 'riscv' variant 'RV64GC' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_riscv_RV64GC.pdf

Description
RISC-V RV64GC 64-bit processor model

Licensing
This Model is released under the Open Source Apache 2.0

Features
The model supports the following architectural features, defined in the misa CSR:
extension A (atomic instructions)
extension C (compressed instructions)
extension D (double-precision floating point)
extension F (single-precision floating point)
RV32I/64I/128I base ISA
extension M (integer multiply/divide instructions)
extension S (Supervisor mode)
extension U (User mode)
64-bit XLEN
If required, supported architectural features may be overridden using parameter "misa_Extensions". Parameter "misa_Extensions_mask" can be used to specify which features can be dynamically enabled or disabled by writes to the misa register.
On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
Values written to "stvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "stvec_mask" if required. parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment in the same manner as for the "mtvec" register, described above.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
A 16-bit ASID is implemented. Use parameter "ASID_bits" to specify a different implemented ASID size if required.
This variant supports address translation modes 0, 8 and 9. Use parameter "Sv_modes" to specify a bit mask of different modes if required.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
16 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit.
LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
By default, the processor starts with floating-point instructions disabled (mstatus.FS=0). Use parameter "mstatus_FS" to force mstatus.FS to a non-zero value for floating-point to be enabled from the start.
The D extension is enabled in this variant independently of the F extension. Set parameter "d_requires_f"to "T" to specify that the D extension requires the F extension to be enabled.
This variant implements floating point status in mstatus.FS as defined in the Privileged Architecture specification. To specify that a simpler mode supporting only values 0 (Off) and 3 (Dirty) should be used, Set parameter "fs_always_dirty" to "T". When this simpler mode is used, any write of values 1 (Initial) or 2 (Clean) from privileged code behave as if value 3 was written.

Interrupts
The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
All other interrupt ports are active high.

Debug Mask
It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support
This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation
If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

LR/SC Active Address
Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.

Limitations
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
The processor fully supports the architecturally-specified floating-point instructions with the exception of the round-to-nearest, ties-to-max-magnitude rounding mode (RMM) which is supported for fcvt instruction variants that convert to long, unsigned long, word, or unsigned word only. In other cases, this rounding mode is treated a round-to-nearest, ties-to-even (RNE). Use of RMM rounding mode in any situation other than rounding to an integral value is dubious because it leads to cumulative bias towards larger-magnitude values.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
The TLB is architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification
All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.

References
The Model details are based upon the following specifications:
---- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.2)
---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.10)

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'hart0' it has been instanced with the following parameters:

Table 3: Processor Instance 'hart0' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips50The nominal MIPS for the processor

Table 4: Processor Instance 'hart0' Parameters (Attributes)

Parameter NameValueType
variantRV64GCenum
reset_address0x1000Uns64


Memory Map for processor 'hart0' bus: 'bus0'
Processor instance 'hart0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'hart0' is connected to bus 'bus0' using master port 'DATA'.

Table 5: Memory Map ( 'hart0' / 'bus0' [width: 48] )

Lo AddressHi AddressInstanceComponent
remappableremappablevirtio_mmio3dynamicDummyPort
remappableremappablevirtio_mmio4dynamicDummyPort
remappableremappablevirtio_mmio5dynamicDummyPort
remappableremappablevirtio_mmio6dynamicDummyPort
remappableremappablevirtio_mmio7dynamicDummyPort
remappableremappablevirtio_mmio8dynamicDummyPort
0x10000x2FFFbootramram
0x20000000x200BFFFclintCLINT
0xC0000000xFFFFFFFplicPLIC
0x100000000x10000007uartTTY016550
0x100010000x100011FFVBD0VirtioBlkMMIO
0x100020000x100021FFVND0VirtioNetMMIO
0x800000000x87FFFFFFmainram


Net Connections to processor: 'hart0'

Table 6: Processor Net Connections ( 'hart0' )

Net PortNetInstanceComponent
MExternalInterruptirqT0plicPLIC
SExternalInterruptirqT1plicPLIC
MTimerInterruptMTimerInterrupt0clintCLINT
MSWInterruptMSWInterrupt0clintCLINT



Peripheral Instances


Peripheral [ovpworld.org/peripheral/VirtioBlkMMIO/1.0] instance: VBD0

Description
VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO block device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf. Use the VB_DRIVE parameter to specify the disk image file to use. Set the VB_DRIVE_DELTA parameter to 1 to prevent writes to disk during simulation from changing the image file.

Limitations
Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing
Open Source Apache 2.0

Reference
http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/VirtioNetMMIO/1.0] instance: VND0

Description
VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO net device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf.

Limitations
Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing
Open Source Apache 2.0

Reference
http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.


Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio3

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 7: Configuration options (attributes) set for instance 'virtio_mmio3'

AttributesValue
portAddress0x10003000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio4

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 8: Configuration options (attributes) set for instance 'virtio_mmio4'

AttributesValue
portAddress0x10004000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio5

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 9: Configuration options (attributes) set for instance 'virtio_mmio5'

AttributesValue
portAddress0x10005000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio6

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 10: Configuration options (attributes) set for instance 'virtio_mmio6'

AttributesValue
portAddress0x10006000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio7

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 11: Configuration options (attributes) set for instance 'virtio_mmio7'

AttributesValue
portAddress0x10007000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/dynamicDummyPort/1.0] instance: virtio_mmio8

Description
dynamicDummyPort - Dynamically open a port and allocate dummy memory region.

Licensing
Open Source Apache 2.0

Limitations
None

Reference
This is not based upon the operation of a real device

Table 12: Configuration options (attributes) set for instance 'virtio_mmio8'

AttributesValue
portAddress0x10008000
portSize4096
cbEnableTrue



Peripheral [riscv.ovpworld.org/peripheral/CLINT/1.0] instance: clint

Licensing
Open Source Apache 2.0

Description
Risc-V Core Local Interruptor (CLINT). Use the num_harts parameter to specify the number of harts suported (default 1). For each supported hart there will be an MTimerInterruptN and MSWInterruptN net port, plus msipN and mtimecmpN registers implemented, where N is a value from 0..num_harts-1 There is also a single mtime register.

Limitations
Writes to mtime register are not supported

Reference
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 13: Configuration options (attributes) set for instance 'clint'

AttributesValue
num_harts1
clockMHz25.0



Peripheral [riscv.ovpworld.org/peripheral/PLIC/1.0] instance: plic

Licensing
Open Source Apache 2.0

Description
PLIC Interrupt Controller

Limitations
Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference
The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 14: Configuration options (attributes) set for instance 'plic'

AttributesValue
num_sources10
num_targets2



Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY0

Licensing
Open Source Apache 2.0

Description
16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

There are no configuration options set for this peripheral instance.


Peripheral [riscv.ovpworld.org/peripheral/SmartLoaderRV64Linux/1.0] instance: smartLoader

Licensing
Open Source Apache 2.0

Description
Psuedo-peripheral to insert boot code for a Riscv 64-bit Linux kernel boot. Loads simulated memory with a device tree blob file and boot code to set regs and jump to a Risc-v Linux Kernel.

Limitations
Only supports little endian

Table 15: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
bootaddr0x80000000
slbootaddr0x1000



Other Sites/Pages with similar information

Information on the virtio Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: VMI Operating System support (VMI OS) API Reference Guide
http://www.ovpworld.org: iGen Model Generator Introduction

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARM Bare Metal Demos Video Presentation
http://www.ovpworld.org: OR1K Demo Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS