Information for XilinxML505

This page provides detailed information about the xilinx.ovpworld.org XilinxML505 Virtual Platform / Virtual Prototype.

Description
Xilinx ML505 Reference Platform

Licensing
Open Source Apache 2.0

Limitations
This platform provides a subset of the full platform functionality. It is provided to boot the Linux operating system. Other software may be used but the operation cannot be guaranteed.

Platform capable of booting linux

Reference
UG347 (v3.1.2) May 16, 2011

Location
The XilinxML505 virtual platform is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / module / XilinxML505 / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Processormicroblaze_0xilinx.ovpworld.orgmicroblaze
PeripheralLEDs_8Bitxilinx.ovpworld.orgxps-gpio
PeripheralIIC_EEPROMxilinx.ovpworld.orgxps-iic
Peripheralxps_intc_0xilinx.ovpworld.orgxps-intc
PeripheralHard_Ethernet_MACxilinx.ovpworld.orgxps-ll-temac
PeripheralSysACE_CompactFlashxilinx.ovpworld.orgxps-sysace
Peripheralxps_timer_1xilinx.ovpworld.orgxps-timer
PeripheralRS232_Uart_1xilinx.ovpworld.orgxps-uartlite
Peripheraldebug_modulexilinx.ovpworld.orgmdm
Peripheralmpmcxilinx.ovpworld.orgmpmc
Peripheralmb_plbxilinx.ovpworld.orgxps-mch-emc
MemoryBOOTMEMovpworld.orgram
MemoryDDR2_SDRAMovpworld.orgram
MemoryUNKNOWN_PERIPHovpworld.orgram
Busbus1(builtin)address width:32



Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: microblaze_0

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'microblaze_0' it has been instanced with the following parameters:

Table 2: Processor Instance 'microblaze_0' Parameters (Configurations)

ParameterValueDescription
endianbigSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips125The nominal MIPS for the processor

Table 3: Processor Instance 'microblaze_0' Parameters (Attributes)

Parameter NameValueType
C_USE_MMU3uns32
C_MMU_ITLB_SIZE2uns32
C_MMU_DTLB_SIZE4uns32
C_MMU_TLB_ACCESS3uns32
C_MMU_ZONES16uns32
C_USE_EXTENDED_FSL_INSTR1bool
C_FSL_EXCEPTION1bool
C_USE_HW_MUL2uns32
C_PVR2uns32
C_OPCODE_0x0_ILLEGAL1bool
C_FPU_EXCEPTION1bool
C_UNALIGNED_EXCEPTIONS1bool
C_ILL_OPCODE_EXCEPTION1bool
C_DIV_ZERO_EXCEPTION1bool
C_INTERCONNECT1uns32
C_USE_BARREL1bool
C_USE_DIV1bool
C_FSL_LINKS4uns32
C_DEBUG_ENABLED1bool
C_I_LMB1bool
C_D_LMB1bool
C_USE_FPU2Uns32
C_USE_MSR_INSTR1bool
C_USE_PCMP_INSTR1bool
C_FAMILY12uns32


Memory Map for processor 'microblaze_0' bus: 'bus1'
Processor instance 'microblaze_0' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'microblaze_0' is connected to bus 'bus1' using master port 'DATA'.

Table 4: Memory Map ( 'microblaze_0' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x1FFFFFFBOOTMEMram
0x814000000x8140FFFFLEDs_8Bitxps-gpio
0x816000000x8160FFFFIIC_EEPROMxps-iic
0x818000000x8180001Fxps_intc_0xps-intc
0x81C000000x81C0003FHard_Ethernet_MACxps-ll-temac
0x836000000x8360FFFFSysACE_CompactFlashxps-sysace
0x83C000000x83C0001Fxps_timer_1xps-timer
0x840000000x8400000FRS232_Uart_1xps-uartlite
0x844000000x8440FFFFdebug_modulemdm
0x846001800x846001FFmpmcmpmc
0x8FFFF0000x8FFFFFFFUNKNOWN_PERIPHram
0x900000000x9FFFFFFFDDR2_SDRAMram
0xA00000000xA1FFFFFFmb_plbxps-mch-emc


Net Connections to processor: 'microblaze_0'

Table 5: Processor Net Connections ( 'microblaze_0' )

Net PortNetInstanceComponent
InterruptInterrupt_netxps_intc_0xps-intc



Peripheral Instances


Peripheral [xilinx.ovpworld.org/peripheral/xps-gpio/1.0] instance: LEDs_8Bit

Description
Microblaze General Purpose IO

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS569 December 2, 2009 v2.00a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-iic/1.0] instance: IIC_EEPROM

Description
Microblaze IIC Bus Interface

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS606 June 22, 2011 v2.03a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-intc/1.0] instance: xps_intc_0

Description
Microblaze LogiCORE IP XPS Interrupt Controller

Licensing
Open Source Apache 2.0

Limitations
This model implements all of the required behavior sufficient to boot Linux

Reference
DS572 April 19, 2010 v2.01a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-ll-temac/1.0] instance: Hard_Ethernet_MAC

Description
Microblaze LogiCORE IP XPS LL TEMAC Ethernet Core

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS537 December 14, 2010 v2.03a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-sysace/1.0] instance: SysACE_CompactFlash

Description
Microblaze LogiCORE SYSACE Interface Controller

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS583 December 2, 2009 v1.01a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-timer/1.0] instance: xps_timer_1

Description
Microblaze LogiCORE IP XPS Timer/Counter

Licensing
Open Source Apache 2.0

Limitations
Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference
DS573 April 19, 2010 v1.02a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-uartlite/1.0] instance: RS232_Uart_1

Description
Xilinx Uart-Lite

Limitations
Register Accurate & Functional Model

Licensing
Open Source Apache 2.0

Reference
DS573 Jun 22, 2011 v1.02.a

Table 6: Configuration options (attributes) set for instance 'RS232_Uart_1'

AttributesValue
outfileRS232_Uart_1.log
finishOnDisconnect1



Peripheral [xilinx.ovpworld.org/peripheral/mdm/1.0] instance: debug_module

Description
Microblaze Debug Module

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS641 July 23, 2010 v2.00.a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/mpmc/1.0] instance: mpmc

Description
Microblaze Multi-Port Memory Controller

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS643 March 1, 2011 v6.03.a

There are no configuration options set for this peripheral instance.


Peripheral [xilinx.ovpworld.org/peripheral/xps-mch-emc/1.0] instance: mb_plb

Description
Microblaze LogiCORE IP XPS MCH EMC Multi Channel External Memory Controller

Licensing
Open Source Apache 2.0

Limitations
This model implements the registers but has no functional behavior

Reference
DS575 June 22, 2010 v3.01a

There are no configuration options set for this peripheral instance.


Other Sites/Pages with similar information

Information on the XilinxML505 Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Simulation Control of Platforms and Modules User Guide
http://www.ovpworld.org: VMI Operating System support (VMI OS) API Reference Guide

Two Videos on these models (from other sites)
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS