Information for Zynq_PL_NoC

This page provides detailed information about the safepower.ovpworld.org Zynq_PL_NoC Virtual Platform / Virtual Prototype.

Licensing
Open Source Apache 2.0

Description
This module implements a configuration for Xilinx Zynq Programmable Logic (PL). This PL configuration instances four Xilinx MicroBlaze processor based NoC sub-systems (Zync_PL_NoC_node), each with a MicroBlaze processor, local memory and NoC interface Peripheral. Also included is a NoC interface peripheral that is accessible from the Zynq_PS ARM processors.

Limitations
This is baremetal only.

Reference
No Reference

Location
The Zynq_PL_NoC virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_NoC / 1.0.

Platform Summary

Table 1: Components in platform

TypeInstanceVendorComponent
Peripheralnodesafepower.ovpworld.orgnode
Memorysmemovpworld.orgram
ModulembNoC1safepower.ovpworld.orgZynq_PL_NoC_node
ModulembNoC2safepower.ovpworld.orgZynq_PL_NoC_node
ModulembNoC3safepower.ovpworld.orgZynq_PL_NoC_node
ModulembNoC4safepower.ovpworld.orgZynq_PL_NoC_node
BusextPortBus(builtin)address width:32
BusmBus(builtin)address width:32
Bridgesmem_extPort(builtin)
Bridgenocif_extPort(builtin)


Platform Simulation Attributes

Table 2: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module Zynq_PL_NoC

Table 3: External Ports

Port TypePort NameInternal Connection
busportextPortextPortBus
netportgpio_bank2_outPgpio_bank2_out
netportgpio_bank2_oen_outPgpio_bank2_oen_out
netportgpio_bank2_inPgpio_bank2_in
netportgpio_bank3_outPgpio_bank3_out
netportgpio_bank3_oen_outPgpio_bank3_oen_out
netportgpio_bank3_inPgpio_bank3_in
netportirqf2p0_outPirqf2p0
netportirqf2p1_outPirqf2p1
netportirqf2p2_outPirqf2p2
netportirqf2p3_outPirqf2p3
netportirqf2p4_outPirqf2p4
netportirqf2p5_outPirqf2p5
netportirqf2p6_outPirqf2p6
netportirqf2p7_outPirqf2p7
netportirqf2p8_outPirqf2p8
netportirqf2p9_outPirqf2p9
netportirqf2p10_outPirqf2p10
netportirqf2p11_outPirqf2p11
netportirqf2p12_outPirqf2p12
netportirqf2p13_outPirqf2p13
netportirqf2p14_outPirqf2p14
netportirqf2p15_outPirqf2p15
netportirqf2p16_outPirqf2p16
netportirqf2p17_outPirqf2p17
netportirqf2p18_outPirqf2p18
netportirqf2p19_outPirqf2p19
netportirqp2f0_inPirqp2f0
netportirqp2f1_inPirqp2f1
netportirqp2f2_inPirqp2f2
netportirqp2f3_inPirqp2f3
netportirqp2f4_inPirqp2f4
netportirqp2f5_inPirqp2f5
netportirqp2f6_inPirqp2f6
netportirqp2f7_inPirqp2f7
netportirqp2f8_inPirqp2f8
netportirqp2f9_inPirqp2f9
netportirqp2f10_inPirqp2f10
netportirqp2f11_inPirqp2f11
netportirqp2f12_inPirqp2f12
netportirqp2f13_inPirqp2f13
netportirqp2f14_inPirqp2f14
netportirqp2f15_inPirqp2f15
netportirqp2f16_inPirqp2f16
netportirqp2f17_inPirqp2f17
netportirqp2f18_inPirqp2f18
netportirqp2f19_inPirqp2f19
netportirqp2f20_inPirqp2f20
netportirqp2f21_inPirqp2f21
netportirqp2f22_inPirqp2f22
netportirqp2f23_inPirqp2f23
netportirqp2f24_inPirqp2f24
netportirqp2f25_inPirqp2f25
netportirqp2f26_inPirqp2f26
netportirqp2f27_inPirqp2f27
netportirqp2f28_inPirqp2f28



Sub-Module [safepower.ovpworld.org/module/Zynq_PL_NoC_node/1.0] instance: mbNoC1

Table 4: Sub-Module Instance 'mbNoC1' Connections

Port TypePort NameConnection
packetnetportnetworkNodePortnetwork



Sub-Module [safepower.ovpworld.org/module/Zynq_PL_NoC_node/1.0] instance: mbNoC2

Table 5: Sub-Module Instance 'mbNoC2' Connections

Port TypePort NameConnection
packetnetportnetworkNodePortnetwork



Sub-Module [safepower.ovpworld.org/module/Zynq_PL_NoC_node/1.0] instance: mbNoC3

Table 6: Sub-Module Instance 'mbNoC3' Connections

Port TypePort NameConnection
packetnetportnetworkNodePortnetwork



Sub-Module [safepower.ovpworld.org/module/Zynq_PL_NoC_node/1.0] instance: mbNoC4

Table 7: Sub-Module Instance 'mbNoC4' Connections

Port TypePort NameConnection
packetnetportnetworkNodePortnetwork



Peripheral Instances


Peripheral [safepower.ovpworld.org/peripheral/node/1.0] instance: node

Description
Example Network on Chip (NoC) node peripheral for SafePower Project

Licensing
Open Source Apache 2.0

Limitations
This model implements a data and control interface to allow a processor to receive or transmit data across a packetnet interface. This is used to illustrate the use as part of a NoC.

Reference
No Reference, created as an example

Table 8: Configuration options (attributes) set for instance 'node'

AttributesValue
id5



Other Sites/Pages with similar information

Information on the Zynq_PL_NoC Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Creating & Using Platforms and Models in C++ with OP API
http://www.ovpworld.org: Creating Behavioral (Peripheral) components using BHM/PPM APIs and adding them to Platforms

Two Videos on these models (from other sites)
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
http://www.ovpworld.org: ARC Demo Video Presentation


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS